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Jürgen Becker 0001
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Publications
- 2006
- [c95]Carlos Morra, M. Sackmann, Sunil Shukla, Jürgen Becker, Reiner W. Hartenstein:
From Equation to VHDL: Using Rewriting Logic for Automated Function Generation. FPL 2006: 1-4 - [c87]Carlos Morra, M. Sackmann, Jürgen Becker, Reiner W. Hartenstein:
Using Rewriting Logic to Generate Different Implementations of Polynomial Approximations in Coarse-Grained Architectures. ReCoSoC 2006: 46-51 - 2005
- [c82]Carlos Morra, Jürgen Becker, Mauricio Ayala-Rincón
, Reiner W. Hartenstein:
FELIX: Using Rewriting-Logic for Generating Functionally Equivalent Implementations. FPL 2005: 25-30 - 2003
- [j5]Jürgen Becker, Reiner W. Hartenstein:
Configware and morphware going mainstream. J. Syst. Archit. 49(4-6): 127-142 (2003) - 1998
- [c24]Jürgen Becker, Reiner W. Hartenstein, Michael Herz, Ulrich Nageldinger:
Parallelization in Co-Compilation for Configurable Accelerators. ASP-DAC 1998: 23-33 - [c18]Jürgen Becker, Reiner W. Hartenstein:
Real-Time Prototyping in Microprocessor/Accelerator Symbiosis. International Workshop on Rapid System Prototyping 1998: 32-38 - 1997
- [c15]Reiner W. Hartenstein, Jürgen Becker, Michael Herz, Ulrich Nageldinger:
A Novel Universal Sequencer Hardware. ARCS 1997: 143-152 - [c14]Reiner W. Hartenstein, Jürgen Becker, Michael Herz, Ulrich Nageldinger:
A Novel Sequencer Hardware for Application Specific Computing. ASAP 1997: 392-401 - [c13]Reiner W. Hartenstein, Jürgen Becker:
Performance Analysis in CoDe-X Partitioning for Structural Programmable Accelerators. CODES 1997: 141-145 - [c12]Reiner W. Hartenstein, Jürgen Becker, Michael Herz, Ulrich Nageldinger:
Data scheduling to increase performance of parallel accelerators. FPL 1997: 294-303 - [c11]Reiner W. Hartenstein, Jürgen Becker:
A Two-level Co-Design Framework for Xputer-based data-driven reconfigurable Accelerators. HICSS (5) 1997: 125-134 - [c10]Reiner W. Hartenstein, Jürgen Becker:
Hardware/Software Co-Design for Data-Driven Xputer-based Accelerators. VLSI Design 1997: 146-150 - 1996
- [j1]Reiner W. Hartenstein, Jürgen Becker, Rainer Kress, Helmut Reinig:
High-performance computing using a reconfigurable accelerator. Concurr. Pract. Exp. 8(6): 429-443 (1996) - [c9]Reiner W. Hartenstein, Jürgen Becker, Michael Herz, Rainer Kress, Ulrich Nageldinger:
A Synthesis System For Bus-Based Wavefront Array Architectures. ASAP 1996: 274-283 - [c8]Reiner W. Hartenstein, Jürgen Becker, Rainer Kress:
Two-level Partitioning of Image Processing Algorithms for the Parallel Map-oriented Machine. CODES 1996: 77-84 - [c7]Reiner W. Hartenstein, Jürgen Becker, Rainer Kress:
Two-Level Hardware/Software Partitioning Using CoDe-X. ECBS 1996: 395- - [c6]Reiner W. Hartenstein, Jürgen Becker, Rainer Kress:
An Embedded Accelerator for Real-Time Image Processing. RTS 1996: 83-88 - [c5]Reiner W. Hartenstein, Jürgen Becker, Rainer Kress:
Custom Computing Machines vs. Hardware/Software Codesign: From a globalized point of view. FPL 1996: 65-76 - [c4]Reiner W. Hartenstein, Jürgen Becker, Michael Herz, Rainer Kress, Ulrich Nageldinger:
A Partitioning Programming Environment for a Novel Parallel Architecture. IPPS 1996: 544-548 - [c3]Reiner W. Hartenstein, Jürgen Becker, Rainer Kress, Helmut Reinig:
CoDe-C: A Novel Two-Level Hardware/Software Co-Design Framework. VLSI Design 1996: 81-84 - 1995
- [c2]Reiner W. Hartenstein, Jürgen Becker, Rainer Kress, Helmut Reinig, Karin Schmidt:
A Parallelizing Compilation Method for the Map-oriented Machine. ASAP 1995: 129-132 - 1994
- [c1]Andreas Ast, Jürgen Becker, Reiner W. Hartenstein, Rainer Kress, Helmut Reinig, Karin Schmidt:
Data-Procedural Languages for FPL-based Machines. FPL 1994: 183-195

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