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ORCIDDavid Z. Pan
David Zhigang Pan
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- affiliation: University of Texas at Austin, USA
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2020 – today
- 2025
[j115]Sepehr Tabrizchi
, Mehrdad Morsali, David Z. Pan, Shaahin Angizi, Arman Roohi:
PINSim: A Processing In- and Near-Sensor Simulator to Model Intelligent Vision Sensors. IEEE Comput. Archit. Lett. 24(1): 17-20 (2025)- [c293]Yao Lai, Sungyoung Lee, Guojin Chen, Souradip Poddar, Mengkang Hu, David Z. Pan, Ping Luo:
AnalogCoder: Analog Circuit Design via Training-Free Code Generation. AAAI 2025: 379-387 - [c292]Hyunsu Chae, Song Hang Chai, Taiyun Chi, Sensen Li, David Z. Pan:
ML-Assisted RF IC Design Enablement: the New Frontier of AI for EDA. ASP-DAC 2025: 683-689 - [c291]David Z. Pan:
Invited: Shaping the Future of Interconnected Physical Design. ISPD 2025: 220-221 - [i71]Shupeng Ning, Hanqing Zhu, Chenghao Feng, Jiaqi Gu, David Z. Pan, Ray T. Chen:
A Hardware-Efficient Photonic Tensor Core: Accelerating Deep Neural Networks with Structured Compression. CoRR abs/2502.01670 (2025) - [i70]Sungyoung Lee, Ziyi Wang, Seunggeun Kim, Taekyun Lee, David Z. Pan:
Self-Supervised Graph Contrastive Pretraining for Device-level Integrated Circuits. CoRR abs/2502.08949 (2025) - [i69]Supriyo Maji, Linran Zhao, Souradip Poddar, David Z. Pan:
Late Breaking Results: Breaking Symmetry- Unconventional Placement of Analog Circuits using Multi-Level Multi-Agent Reinforcement Learning. CoRR abs/2503.22958 (2025) - [i68]Wenyan Cong, Hanqing Zhu, Peihao Wang, Bangya Liu, Dejia Xu, Kevin Wang, David Z. Pan, Yan Wang, Zhiwen Fan, Zhangyang Wang:
Can Test-Time Scaling Improve World Foundation Model? CoRR abs/2503.24320 (2025) - 2024
- [j114]Xiaohan Gao, Haoyi Zhang, Siyuan Ye, Mingjie Liu, David Z. Pan, Linxiao Shen, Runsheng Wang, Yibo Lin, Ru Huang:
Post-layout simulation driven analog circuit sizing. Sci. China Inf. Sci. 67(4) (2024) - [j113]Hyunsu Chae, Keren Zhu, Bhyrav Mutnury, Douglas Wallace, Douglas Winterberg, Daniel De Araujo, Jay Reddy, Adam R. Klivans, David Z. Pan:
ISOP+: Machine Learning-Assisted Inverse Stack-Up Optimization for Advanced Package Design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43(1): 2-15 (2024) - [j112]Arman Roohi, Sepehr Tabrizchi, Mehrdad Morsali, David Z. Pan, Shaahin Angizi:
PiPSim: A Behavior-Level Modeling Tool for CNN Processing-in-Pixel Accelerators. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43(1): 141-150 (2024) - [j111]Guojin Chen, Zixiao Wang, Bei Yu, David Z. Pan, Martin D. F. Wong:
Ultrafast Source Mask Optimization via Conditional Discrete Diffusion. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43(7): 2140-2150 (2024) - [c290]Chen-Hao Hsu, Xiaoqing Xu, Hao Chen, Dino Ruic, David Z. Pan:
TransPlace: A Scalable Transistor-Level Placer for VLSI Beyond Standard-Cell-Based Design. ASPDAC 2024: 312-318 - [c289]Hyunsu Chae, Keren Zhu, Bhyrav Mutnury, Zixuan Jiang, Daniel De Araujo, Douglas Wallace, Douglas Winterberg, Adam R. Klivans, David Z. Pan:
ISOP-Yield: Yield-Aware Stack-Up Optimization for Advanced Package using Machine Learning. ASPDAC 2024: 644-650 - [c288]Supriyo Maji, Ahmet Faruk Budak, Souradip Poddar, David Z. Pan:
Toward End-to-End Analog Design Automation with ML and Data-Driven Approaches (Invited Paper). ASPDAC 2024: 657-664 - [c287]Supriyo Maji, Sungyoung Lee, David Z. Pan:
Analog Transistor Placement Optimization Considering Nonlinear Spatial Variations. DATE 2024: 1-6 - [c286]Souradip Poddar, Ahmet Faruk Budak, Linran Zhao, Chen-Hao Hsu, Supriyo Maji, Keren Zhu, Yaoyao Jia, David Z. Pan:
A Data-Driven Analog Circuit Synthesizer with Automatic Topology Selection and Sizing. DATE 2024: 1-6 - [c285]Hanchen Ye, David Z. Pan, Chris Leary, Deming Chen, Xiaoqing Xu:
Subgraph Extraction-Based Feedback-Guided Iterative Scheduling for HLS. DATE 2024: 1-6 - [c284]Zhili Xiong, Rachel Selina Rajarathnam, David Z. Pan:
A Data-Driven, Congestion-Aware and Open-Source Timing-Driven FPGA Placer Accelerated by GPUs. FCCM 2024: 115-125 - [c283]Rachel Selina Rajarathnam, Kate Thurmer, Vaughn Betz, Mahesh A. Iyer, David Z. Pan:
Better Together: Combining Analytical and Annealing Methods for FPGA Placement. FPL 2024: 43-52 - [c282]Sepehr Tabrizchi, Nedasadat Taheri, Justin Feng, Nader Sehatbakhsh, David Z. Pan, Arman Roohi:
SRC: Sustainable Reactive Computing for Battery-free Edge Intelligence. IGSC 2024: 93-98 - [c281]Hanqing Zhu, Jiaqi Gu, Hanrui Wang, Zixuan Jiang, Zhekai Zhang, Rongxing Tang, Chenghao Feng, Song Han, Ray T. Chen, David Z. Pan:
Lightening-Transformer: A Dynamically-Operated Optically-Interconnected Photonic Transformer Accelerator. HPCA 2024: 686-703 - [c280]Guojin Chen, Haoyu Yang, Haoxing Mark Ren, Bei Yu, David Z. Pan:
Differentiable Edge-based OPC. ICCAD 2024: 47:1-47:9 - [c279]Hyunsu Chae, Hao Yu, Sensen Li, David Z. Pan:
PulseRF: Physics Augmented ML Modeling and Synthesis for High-Frequency RFIC Design. ICCAD 2024: 163:1-163:9 - [c278]Hanrui Wang, Pengyu Liu, Daniel Bochen Tan, Yilian Liu, Jiaqi Gu, David Z. Pan, Jason Cong, Umut A. Acar, Song Han:
Atomique: A Quantum Compiler for Reconfigurable Neutral Atom Arrays. ISCA 2024: 293-309 - [c277]Ruisi Zhang, Rachel Selina Rajarathnam, David Z. Pan, Farinaz Koushanfar:
Automated Physical Design Watermarking Leveraging Graph Neural Networks. MLCAD 2024: 13:1-13:10 - [c276]Yao Lai, Jinxin Liu, David Z. Pan, Ping Luo:
Scalable and Effective Arithmetic Tree Generation for Adder and Multiplier Designs. NeurIPS 2024 - [c275]Hanqing Zhu, Wenyan Cong, Guojin Chen, Shupeng Ning, Ray T. Chen, Jiaqi Gu, David Z. Pan:
PACE: Pacing Operator Learning to Accurate Optical Field Simulation for Complicated Photonic Devices. NeurIPS 2024 - [i67]Tianlong Chen, Zhenyu Zhang, Hanrui Wang, Jiaqi Gu, Zirui Li, David Z. Pan, Frederic T. Chong, Song Han, Zhangyang Wang:
QuantumSEA: In-Time Sparse Exploration for Noise Adaptive Quantum Circuits. CoRR abs/2401.05571 (2024) - [i66]Hanchen Ye, David Z. Pan, Chris Leary, Deming Chen, Xiaoqing Xu:
Subgraph Extraction-based Feedback-guided Iterative Scheduling for HLS. CoRR abs/2401.12343 (2024) - [i65]Shupeng Ning, Hanqing Zhu, Chenghao Feng, Jiaqi Gu, Zhixing Jiang, Zhoufeng Ying, Jason Midkiff, Sourabh Jain, May H. Hlaing, David Z. Pan, Ray T. Chen:
Photonic-Electronic Integrated Circuits for High-Performance Computing and AI Accelerator. CoRR abs/2403.14806 (2024) - [i64]Ruisi Zhang, Rachel Selina Rajarathnam, David Z. Pan, Farinaz Koushanfar:
ICMarks: A Robust Watermarking Framework for Integrated Circuit Physical Design IP Protection. CoRR abs/2404.18407 (2024) - [i63]Yao Lai, Jinxin Liu, David Z. Pan, Ping Luo:
Scalable and Effective Arithmetic Tree Generation for Adder and Multiplier Designs. CoRR abs/2405.06758 (2024) - [i62]Yao Lai, Sungyoung Lee, Guojin Chen, Souradip Poddar, Mengkang Hu, David Z. Pan, Ping Luo:
AnalogCoder: Analog Circuit Design via Training-Free Code Generation. CoRR abs/2405.14918 (2024) - [i61]Guojin Chen, Keren Zhu, Seunggeun Kim, Hanqing Zhu, Yao Lai, Bei Yu, David Z. Pan:
LLM-Enhanced Bayesian Optimization for Efficient Analog Layout Constraint Generation. CoRR abs/2406.05250 (2024) - [i60]Supriyo Maji, Hyungjoo Park, Gi moon Hong, Souradip Poddar, David Z. Pan:
Multi-Objective Optimization for Common-Centroid Placement of Analog Transistors. CoRR abs/2407.00817 (2024) - [i59]Souradip Poddar, Youngmin Oh, Yao Lai, Hanqing Zhu, Bosun Hwang, David Z. Pan:
INSIGHT: Universal Neural Simulator for Analog Circuits Harnessing Autoregressive Transformers. CoRR abs/2407.07346 (2024) - [i58]Ruisi Zhang, Rachel Selina Rajarathnam, David Z. Pan, Farinaz Koushanfar:
Automated Physical Design Watermarking Leveraging Graph Neural Networks. CoRR abs/2407.20544 (2024) - [i57]Guojin Chen, Haoyu Yang, Haoxing Ren, Bei Yu, David Z. Pan:
Differentiable Edge-based OPC. CoRR abs/2408.08969 (2024) - [i56]Guojin Chen, Hao Geng, Bei Yu, David Z. Pan:
Open-Source Differentiable Lithography Imaging Framework. CoRR abs/2409.15306 (2024) - [i55]Hanqing Zhu, Wenyan Cong, Guojin Chen, Shupeng Ning, Ray T. Chen, Jiaqi Gu, David Z. Pan:
PACE: Pacing Operator Learning to Accurate Optical Field Simulation for Complicated Photonic Devices. CoRR abs/2411.03527 (2024) - [i54]Youngmin Oh, Jinje Park, Seunggeun Kim, Taejin Paik, David Z. Pan, Bosun Hwang:
M3: Mamba-assisted Multi-Circuit Optimization via MBRL with Effective Scheduling. CoRR abs/2411.16019 (2024) - [i53]Hanqing Zhu, Zhenyu Zhang, Wenyan Cong, Xi Liu, Sem Park, Vikas Chandra, Bo Long, David Z. Pan, Zhangyang Wang, Jinwon Lee:
APOLLO: SGD-like Memory, AdamW-level Performance. CoRR abs/2412.05270 (2024) - 2023
- [j110]Xiangxing Yang, Keren Zhu, Xiyuan Tang, Meizhi Wang, Mingtao Zhan, Nanshu Lu, Jaydeep P. Kulkarni, David Z. Pan, Yongpan Liu, Nan Sun:
An In-Memory-Computing Charge-Domain Ternary CNN Classifier. IEEE J. Solid State Circuits 58(5): 1450-1461 (2023) - [j109]Xiyuan Tang, Xiangxing Yang, Jiaxin Liu, Zongnan Wang, Wei Shi, David Z. Pan, Nan Sun:
A Bandwidth-Adaptive Pipelined SAR ADC With Three-Stage Cascoded Floating Inverter Amplifier. IEEE J. Solid State Circuits 58(9): 2564-2574 (2023) - [j108]Xiaohan Gao, Haoyi Zhang, Mingjie Liu, Linxiao Shen, David Z. Pan, Yibo Lin, Runsheng Wang, Ru Huang:
Interactive Analog Layout Editing With Instant Placement and Routing Legalization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(3): 698-711 (2023) - [j107]Jiaqi Gu, Chenghao Feng, Hanqing Zhu, Zheng Zhao, Zhoufeng Ying, Mingjie Liu, Ray T. Chen, David Z. Pan:
SqueezeLight: A Multi-Operand Ring-Based Optical Neural Network With Cross-Layer Scalability. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(3): 807-819 (2023) - [j106]Hanqing Zhu, Jiaqi Gu, Chenghao Feng, Mingjie Liu, Zixuan Jiang, Ray T. Chen, David Z. Pan:
ELight: Toward Efficient and Aging-Resilient Photonic In-Memory Neurocomputing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(3): 820-833 (2023) - [j105]Keren Zhu, Hao Chen, Mingjie Liu, David Z. Pan:
Hierarchical Analog and Mixed-Signal Circuit Placement Considering System Signal Flow. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(8): 2689-2702 (2023) - [j104]Keren Zhu, Hao Chen, Mingjie Liu, David Z. Pan:
Tutorial and Perspectives on MAGICAL: A Silicon-Proven Open-Source Analog IC Layout System. IEEE Trans. Circuits Syst. II Express Briefs 70(2): 715-720 (2023) - [j103]Shaahin Angizi, Sepehr Tabrizchi, David Z. Pan, Arman Roohi:
PISA: A Non-Volatile Processing-in-Sensor Accelerator for Imaging Systems. IEEE Trans. Emerg. Top. Comput. 11(4): 962-972 (2023) - [c274]Ahmet Faruk Budak, David Smart, Brian Swahn, David Z. Pan:
APOSTLE: Asynchronously Parallel Optimization for Sizing Analog Transistors Using DNN Learning. ASP-DAC 2023: 70-75 - [c273]Zixuan Jiang, Jiaqi Gu, Mingjie Liu, David Z. Pan:
Delving into Effective Gradient Matching for Dataset Condensation. COINS 2023: 1-6 - [c272]Zixuan Jiang, Jiaqi Gu, David Z. Pan:
NormSoftmax: Normalizing the Input of Softmax to Accelerate and Stabilize Training. COINS 2023: 1-6 - [c271]Hyunsu Chae, Bhyrav Mutnury, Keren Zhu, Douglas Wallace, Douglas Winterberg, Daniel De Araujo, Jay Reddy, Adam R. Klivans, David Z. Pan:
ISOP: Machine Learning-Assisted Inverse Stack-Up Optimization for Advanced Package Design. DATE 2023: 1-6 - [c270]Ahmet Faruk Budak, Keren Zhu, David Z. Pan:
Practical Layout-Aware Analog/Mixed-Signal Design Automation with Bayesian Neural Networks. ICCAD 2023: 1-8 - [c269]Hao Chen, Kai-Chieh Hsu, Walker J. Turner, Po-Hsuan Wei, Keren Zhu, David Z. Pan, Haoxing Ren:
Reinforcement Learning Guided Detailed Routing for Custom Circuits. ISPD 2023: 26-34 - [c268]Ahmet Faruk Budak, Keren Zhu, Hao Chen, Souradip Poddar, Linran Zhao, Yaoyao Jia, David Z. Pan:
Joint Optimization of Sizing and Layout for AMS Designs: Challenges and Opportunities. ISPD 2023: 84-92 - [c267]Rachel Selina Rajarathnam, Zixuan Jiang, Mahesh A. Iyer, David Z. Pan:
DREAMPlaceFPGA-PL: An Open-Source GPU-Accelerated Packer-Legalizer for Heterogeneous FPGAs. ISPD 2023: 175-184 - [c266]Zixuan Jiang, Jiaqi Gu, Hanqing Zhu, David Z. Pan:
Pre-RMSNorm and Pre-CRMSNorm Transformers: Equivalent and Efficient Pre-LN Transformers. NeurIPS 2023 - [c265]Tianlong Chen, Zhenyu Zhang, Hanrui Wang, Jiaqi Gu, Zirui Li, David Z. Pan, Frederic T. Chong, Song Han, Zhangyang Wang:
QuantumSEA: In-Time Sparse Exploration for Noise Adaptive Quantum Circuits. QCE 2023: 51-62 - [i52]Zixuan Jiang, Jiaqi Gu, Hanqing Zhu, David Z. Pan:
Pre-RMSNorm and Pre-CRMSNorm Transformers: Equivalent and Efficient Pre-LN Transformers. CoRR abs/2305.14858 (2023) - [i51]Jiaqi Gu, Hanqing Zhu, Chenghao Feng, Zixuan Jiang, Ray T. Chen, David Z. Pan:
M3ICRO: Machine Learning-Enabled Compact Photonic Tensor Core based on PRogrammable Multi-Operand Multimode Interference. CoRR abs/2305.19505 (2023) - [i50]Hanqing Zhu, Jiaqi Gu, Hanrui Wang, Zixuan Jiang, Zhekai Zhang, Rongxin Tang, Chenghao Feng, Song Han, Ray T. Chen, David Z. Pan:
DOTA: A Dynamically-Operated Photonic Tensor Core for Energy-Efficient Transformer Accelerator. CoRR abs/2305.19533 (2023) - [i49]Chenghao Feng, Jiaqi Gu, Hanqing Zhu, Rongxing Tang, Shupeng Ning, May Hlaing, Jason Midkiff, Sourabh Jain, David Z. Pan, Ray T. Chen:
Integrated multi-operand optical neurons for scalable and hardware-efficient deep learning. CoRR abs/2305.19592 (2023) - [i48]Xiaohan Gao, Haoyi Zhang, Siyuan Ye, Mingjie Liu, David Z. Pan, Linxiao Shen, Runsheng Wang, Yibo Lin, Ru Huang:
Post-Layout Simulation Driven Analog Circuit Sizing. CoRR abs/2310.14049 (2023) - [i47]Zhili Xiong, Rachel Selina Rajarathnam, Zhixing Jiang, Hanqing Zhu, David Z. Pan:
DREAMPlaceFPGA-MP: An Open-Source GPU-Accelerated Macro Placer for Modern FPGAs with Cascade Shapes and Region Constraints. CoRR abs/2311.08582 (2023) - [i46]Hanrui Wang, Pengyu Liu, Bochen Tan, Yilian Liu, Jiaqi Gu, David Z. Pan, Jason Cong, Umut A. Acar, Song Han:
FPQA-C: A Compilation Framework for Field Programmable Qubit Array. CoRR abs/2311.15123 (2023) - [i45]Hanrui Wang, Yilian Liu, Pengyu Liu, Jiaqi Gu, Zirui Li, Zhiding Liang, Jinglei Cheng, Yongshan Ding, Xuehai Qian, Yiyu Shi, David Z. Pan, Frederic T. Chong, Song Han:
RobustState: Boosting Fidelity of Quantum State Preparation via Noise-Aware Variational Training. CoRR abs/2311.16035 (2023) - [i44]Hanrui Wang, Pengyu Liu, Kevin Shao, Dantong Li, Jiaqi Gu, David Z. Pan, Yongshan Ding, Song Han:
Transformer-QEC: Quantum Error Correction Code Decoding with Transferable Transformers. CoRR abs/2311.16082 (2023) - [i43]Ahmet Faruk Budak, Keren Zhu, David Z. Pan:
Practical Layout-Aware Analog/Mixed-Signal Design Automation with Bayesian Neural Networks. CoRR abs/2311.17073 (2023) - 2022
- [j102]Ki Yong Kim, David Z. Pan, Ranjit Gharpurey:
A Broadband Spectrum Channelizer With PWM-LO-Based Sub-Band Gain Control. IEEE J. Solid State Circuits 57(3): 781-792 (2022) - [j101]Yibai Meng, Wuxi Li, Yibo Lin, David Z. Pan:
elfPlace: Electrostatics-Based Placement for Large-Scale Heterogeneous FPGAs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(1): 155-168 (2022) - [j100]Ahmet Faruk Budak, Miguel Gandara, Wei Shi, David Z. Pan, Nan Sun, Bo Liu:
An Efficient Analog Circuit Sizing Method Based on Machine Learning Assisted Global Optimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(5): 1209-1221 (2022) - [j99]Martin Rapp, Hussam Amrouch, Yibo Lin, Bei Yu, David Z. Pan, Marilyn Wolf, Jörg Henkel:
MLCAD: A Survey of Research in Machine Learning for CAD Keynote Paper. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(10): 3162-3181 (2022) - [j98]Jiaqi Gu, Chenghao Feng, Hanqing Zhu, Ray T. Chen, David Z. Pan:
Light in AI: Toward Efficient Neurocomputing With Optical Neural Networks - A Tutorial. IEEE Trans. Circuits Syst. II Express Briefs 69(6): 2581-2585 (2022) - [c264]Keren Zhu, Hao Chen, Mingjie Liu, David Z. Pan:
Automating Analog Constraint Extraction: From Heuristics to Learning: (Invited Paper). ASP-DAC 2022: 108-113 - [c263]Rachel Selina Rajarathnam, Mohamed Baker Alawieh, Zixuan Jiang, Mahesh A. Iyer, David Z. Pan:
DREAMPlaceFPGA: An Open-Source Analytical Placer for Large Scale Heterogeneous FPGAs using Deep-Learning Toolkit. ASP-DAC 2022: 300-306 - [c262]Hanqing Zhu, Jiaqi Gu, Chenghao Feng, Mingjie Liu, Zixuan Jiang, Ray T. Chen, David Z. Pan:
ELight: Enabling Efficient Photonic In-Memory Neurocomputing with Life Enhancement. ASP-DAC 2022: 332-338 - [c261]Ahmet Faruk Budak, Zixuan Jiang, Keren Zhu, Azalia Mirhoseini, Anna Goldie, David Z. Pan:
Reinforcement Learning for Electronic Design Automation: Case Studies and Perspectives: (Invited Paper). ASP-DAC 2022: 500-505 - [c260]Keren Zhu, Hao Chen, Mingjie Liu, Xiyuan Tang, Wei Shi, Nan Sun, David Z. Pan:
Generative-Adversarial-Network-Guided Well-Aware Placement for Analog Circuits. ASP-DAC 2022: 519-525 - [c259]Jiaqi Gu, Hyoukjun Kwon, Dilin Wang, Wei Ye, Meng Li, Yu-Hsin Chen, Liangzhen Lai, Vikas Chandra, David Z. Pan:
Multi-Scale High-Resolution Vision Transformer for Semantic Segmentation. CVPR 2022: 12084-12093 - [c258]Hanrui Wang, Jiaqi Gu, Yongshan Ding, Zirui Li, Frederic T. Chong, David Z. Pan, Song Han:
QuantumNAT: quantum noise-aware training with noise injection, quantization and normalization. DAC 2022: 1-6 - [c257]Hanrui Wang, Zirui Li, Jiaqi Gu, Yongshan Ding, David Z. Pan, Song Han:
QOC: quantum on-chip training with parameter shift and gradient pruning. DAC 2022: 655-660 - [c256]Jiaqi Gu, Hanqing Zhu, Chenghao Feng, Zixuan Jiang, Mingjie Liu, Shuhan Zhang, Ray T. Chen, David Z. Pan:
ADEPT: automatic differentiable DEsign of photonic tensor cores. DAC 2022: 937-942 - [c255]Zizheng Guo, Mingjie Liu, Jiaqi Gu, Shuhan Zhang, David Z. Pan, Yibo Lin:
A timing engine inspired graph neural network model for pre-routing slack prediction. DAC 2022: 1207-1212 - [c254]Hao Chen, Walker J. Turner, David Z. Pan, Haoxing Ren:
Routability-Aware Placement for Advanced FinFET Mixed-Signal Circuits using Satisfiability Modulo Theories. DATE 2022: 160-165 - [c253]Hanrui Wang, Yongshan Ding, Jiaqi Gu, Yujun Lin, David Z. Pan, Frederic T. Chong, Song Han:
QuantumNAS: Noise-Adaptive Search for Robust Quantum Circuits. HPCA 2022: 692-708 - [c252]Hanqing Zhu, Keren Zhu, Jiaqi Gu, Harrison Jin, Ray T. Chen, Jean Anne C. Incorvia, David Z. Pan:
Fuse and Mix: MACAM-Enabled Analog Activation for Energy-Efficient Neural Acceleration. ICCAD 2022: 37:1-37:9 - [c251]Keren Zhu, Hao Chen, Walker J. Turner, George F. Kokai, Po-Hsuan Wei, David Z. Pan, Haoxing Ren:
TAG: Learning Circuit Spatial Embedding from Layouts. ICCAD 2022: 66:1-66:9 - [c250]Hanrui Wang, Zhiding Liang, Jiaqi Gu, Zirui Li, Yongshan Ding, Weiwen Jiang, Yiyu Shi, David Z. Pan, Frederic T. Chong, Song Han:
TorchQuantum Case Study for Robust Quantum Circuits. ICCAD 2022: 136:1-136:9 - [c249]David Z. Pan:
EDAML 2022 Keynote Speaker: Machine Learning for Agile, Intelligent and Open-Source EDA. IPDPS Workshops 2022: 1181 - [c248]Hao Chen, Walker J. Turner, Sanquan Song, Keren Zhu, George F. Kokai, Brian Zimmer, C. Thomas Gray, Brucek Khailany, David Z. Pan, Haoxing Ren:
AutoCRAFT: Layout Automation for Custom Circuits in Advanced FinFET Technologies. ISPD 2022: 175-183 - [c247]Gracieli Posser, Evangeline F. Y. Young, Stephan Held, Yih-Lang Li, David Z. Pan:
Challenges and Approaches in VLSI Routing. ISPD 2022: 185-192 - [c246]Wei Shi, Hanrui Wang, Jiaqi Gu, Mingjie Liu, David Z. Pan, Song Han, Nan Sun:
RobustAnalog: Fast Variation-Aware Analog Circuit Design Via Multi-task RL. MLCAD 2022: 35-41 - [c245]Zixuan Jiang, Mingjie Liu, Zizheng Guo, Shuhan Zhang, Yibo Lin, David Z. Pan:
A Tale of EDA's Long Tail: Long-Tailed Distribution Learning for Electronic Design Automation. MLCAD 2022: 135-141 - [c244]Jiaqi Gu, Zhengqi Gao, Chenghao Feng, Hanqing Zhu, Ray T. Chen, Duane S. Boning, David Z. Pan:
NeurOLight: A Physics-Agnostic Neural Operator Enabling Parametric Photonic Device Simulation. NeurIPS 2022 - [i42]Hanrui Wang, Zirui Li, Jiaqi Gu, Yongshan Ding, David Z. Pan, Song Han:
On-chip QNN: Towards Efficient On-Chip Training of Quantum Neural Networks. CoRR abs/2202.13239 (2022) - [i41]Wei Shi, Hanrui Wang, Jiaqi Gu, Mingjie Liu, David Z. Pan, Song Han, Nan Sun:
RobustAnalog: Fast Variation-Aware Analog Circuit Design Via Multi-task RL. CoRR abs/2207.06412 (2022) - [i40]Zixuan Jiang, Jiaqi Gu, Mingjie Liu, David Z. Pan:
Delving into Effective Gradient Matching for Dataset Condensation. CoRR abs/2208.00311 (2022) - [i39]Wei Li, Ruxuan Li, Yuzhe Ma, Siu On Chan, David Z. Pan, Bei Yu:
Rethinking Graph Neural Networks for the Graph Coloring Problem. CoRR abs/2208.06975 (2022) - [i38]Hanqing Zhu, Keren Zhu, Jiaqi Gu, Harrison Jin, Ray T. Chen, Jean Anne C. Incorvia, David Z. Pan:
Fuse and Mix: MACAM-Enabled Analog Activation for Energy-Efficient Neural Acceleration. CoRR abs/2208.08099 (2022) - [i37]Keren Zhu, Hao Chen, Walker J. Turner, George F. Kokai, Po-Hsuan Wei, David Z. Pan, Haoxing Ren:
TAG: Learning Circuit Spatial Embedding From Layouts. CoRR abs/2209.03465 (2022) - [i36]Jiaqi Gu, Zhengqi Gao, Chenghao Feng, Hanqing Zhu, Ray T. Chen, Duane S. Boning, David Z. Pan:
NeurOLight: A Physics-Agnostic Neural Operator Enabling Parametric Photonic Device Simulation. CoRR abs/2209.10098 (2022) - [i35]Mingjie Liu, Haoyu Yang, Zongyi Li, Kumara Sastry, Saumyadip Mukhopadhyay, Selim Dogru, Anima Anandkumar, David Z. Pan, Brucek Khailany, Haoxing Ren:
An Adversarial Active Sampling-based Data Augmentation Framework for Manufacturable Chip Design. CoRR abs/2210.15765 (2022) - [i34]Hanrui Wang, Pengyu Liu, Jinglei Cheng, Zhiding Liang, Jiaqi Gu, Zirui Li, Yongshan Ding, Weiwen Jiang, Yiyu Shi, Xuehai Qian, David Z. Pan, Frederic T. Chong, Song Han:
QuEst: Graph Transformer for Quantum Circuit Reliability Estimation. CoRR abs/2210.16724 (2022) - [i33]Jiaqi Gu, Ben Keller, Jean Kossaifi, Anima Anandkumar, Brucek Khailany, David Z. Pan:
HEAT: Hardware-Efficient Automatic Tensor Decomposition for Transformer Compression. CoRR abs/2211.16749 (2022) - 2021
- [j97]Hao Chen, Mingjie Liu, Biying Xu, Keren Zhu, Xiyuan Tang, Shaolan Li, Yibo Lin, Nan Sun, David Z. Pan:
MAGICAL: An Open- Source Fully Automated Analog IC Layout System from Netlist to GDSII. IEEE Des. Test 38(2): 19-26 (2021) - [j96]Mohamed Baker Alawieh, Yibo Lin, Zaiwei Zhang, Meng Li, Qixing Huang, David Z. Pan:
GAN-SRAF: Subresolution Assist Feature Generation Using Generative Adversarial Networks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40(2): 373-385 (2021) - [j95]Junzhe Cai, Changhao Yan, Yudong Tao, Yibo Lin, Sheng-Guo Wang, David Z. Pan, Xuan Zeng:
A Novel and Unified Full-Chip CMP Model Aware Dummy Fill Insertion Framework With SQP-Based Optimization Method. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40(3): 603-607 (2021) - [j94]Yibo Lin, Zixuan Jiang, Jiaqi Gu, Wuxi Li, Shounak Dhar, Haoxing Ren, Brucek Khailany, David Z. Pan:
DREAMPlace: Deep Learning Toolkit-Enabled GPU Acceleration for Modern VLSI Placement. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40(4): 748-761 (2021) - [j93]Jiaqi Gu, Zheng Zhao, Chenghao Feng, Zhoufeng Ying, Mingjie Liu, Ray T. Chen, David Z. Pan:
Toward Hardware-Efficient Optical Neural Networks: Beyond FFT Architecture via Joint Learnability. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40(9): 1796-1809 (2021) - [j92]Wei Li, Yuzhe Ma, Qi Sun, Lu Zhang, Yibo Lin, Iris Hui-Ru Jiang, Bei Yu, David Z. Pan:
OpenMPL: An Open-Source Layout Decomposer. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40(11): 2331-2344 (2021) - [c243]Jiaqi Gu, Chenghao Feng, Zheng Zhao, Zhoufeng Ying, Ray T. Chen, David Z. Pan:
Efficient On-Chip Learning for Optical Neural Networks Through Power-Aware Sparse Zeroth-Order Optimization. AAAI 2021: 7583-7591 - [c242]Xiaohan Gao, Chenhui Deng, Mingjie Liu, Zhiru Zhang, David Z. Pan, Yibo Lin:
Layout Symmetry Annotation for Analog Circuits with Graph Neural Networks. ASP-DAC 2021: 152-157 - [c241]Hao Chen, Mingjie Liu, Xiyuan Tang, Keren Zhu, Abhishek Mukherjee, Nan Sun, David Z. Pan:
MAGICAL 1.0: An Open-Source Fully-Automated AMS Layout Synthesis Framework Verified With a 40-nm 1GS/s Δ∑ ADC. CICC 2021: 1-2 - [c240]Xiangxing Yang, Keren Zhu, Xiyuan Tang, Meizhi Wang, Mingtao Zhan, Nanshu Lu, Jaydeep P. Kulkarni, David Z. Pan, Yongpan Liu, Nan Sun:
An In-Memory-Computing Charge-Domain Ternary CNN Classifier. CICC 2021: 1-2 - [c239]Ahmet Faruk Budak, Prateek Bhansali, Bo Liu, Nan Sun, David Z. Pan, Chandramouli V. Kashyap:
DNN-Opt: An RL Inspired Optimization for Analog Circuit Sizing using Deep Neural Networks. DAC 2021: 1219-1224 - [c238]Hao Chen, Keren Zhu, Mingjie Liu, Xiyuan Tang, Nan Sun, David Z. Pan:
Universal Symmetry Constraint Extraction for Analog and Mixed-Signal Circuits with Graph Neural Networks. DAC 2021: 1243-1248 - [c237]Xiaohan Gao, Mingjie Liu, David Z. Pan, Yibo Lin:
Interactive Analog Layout Editing with Instant Placement Legalization. DAC 2021: 1249-1254 - [c236]Jiaqi Gu, Chenghao Feng, Zheng Zhao, Zhoufeng Ying, Mingjie Liu, Ray T. Chen, David Z. Pan:
SqueezeLight: Towards Scalable Optical Neural Networks with Multi-Operand Ring Resonators. DATE 2021: 238-243 - [c235]Shubham Rai, Walter Lau Neto, Yukio Miyasaka, Xinpei Zhang, Mingfei Yu, Qingyang Yi, Masahiro Fujita, Guilherme B. Manske, Matheus F. Pontes, Leomar S. da Rosa, Marilton S. de Aguiar, Paulo F. Butzen, Po-Chun Chien, Yu-Shan Huang, Hoa-Ren Wang, Jie-Hong R. Jiang, Jiaqi Gu, Zheng Zhao, Zixuan Jiang, David Z. Pan, Brunno A. Abreu, Isac de Souza Campos, Augusto Andre Souza Berndt, Cristina Meinhardt, Jônata Tyska Carvalho, Mateus Grellert, Sergio Bampi, Aditya Lohana, Akash Kumar, Wei Zeng, Azadeh Davoodi, Rasit Onur Topaloglu, Yuan Zhou, Jordan Dotzel, Yichi Zhang, Hanyu Wang, Zhiru Zhang, Valerio Tenace, Pierre-Emmanuel Gaillardon, Alan Mishchenko, Satrajit Chatterjee:
Logic Synthesis Meets Machine Learning: Trading Exactness for Generalization. DATE 2021: 1026-1031 - [c234]Jiaqi Gu, Zheng Zhao, Chenghao Feng, Zhoufeng Ying, Ray T. Chen, David Z. Pan:
O2NN: Optical Neural Networks with Differential Detection-Enabled Optical Operands. DATE 2021: 1062-1067 - [c233]Mingjie Liu, Walker J. Turner, George F. Kokai, Brucek Khailany, David Z. Pan, Haoxing Ren:
Parasitic-Aware Analog Circuit Sizing with Graph Neural Networks and Bayesian Optimization. DATE 2021: 1372-1377 - [c232]Mingjie Liu, Xiyuan Tang, Keren Zhu, Hao Chen, Nan Sun, David Z. Pan:
OpenSAR: An Open Source Automated End-to-end SAR ADC Compiler. ICCAD 2021: 1-9 - [c231]Jiaqi Gu, Hanqing Zhu, Chenghao Feng, Mingjie Liu, Zixuan Jiang, Ray T. Chen, David Z. Pan:
Towards Memory-Efficient Neural Networks via Multi-Level in situ Generation. ICCV 2021: 5209-5218 - [c230]Xiyuan Tang, Xiangxing Yang, Jiaxin Liu, Wei Shi, David Z. Pan, Nan Sun:
A 0.4-to-40MS/s 75.7dB-SNDR Fully Dynamic Event-Driven Pipelined ADC with 3-Stage Cascoded Floating Inverter Amplifier. ISSCC 2021: 376-378 - [c229]Mohamed Baker Alawieh, David Z. Pan:
ADAPT: An Adaptive Machine Learning Framework with Application to Lithography Hotspot Detection. MLCAD 2021: 1-6 - [c228]Zixuan Jiang, Ebrahim M. Songhori, Shen Wang, Anna Goldie, Azalia Mirhoseini, Joe W. J. Jiang, Young-Joon Lee, David Z. Pan:
Delving into Macro Placement with Reinforcement Learning. MLCAD 2021: 1-3 - [c227]Jiaqi Gu, Hanqing Zhu, Chenghao Feng, Zixuan Jiang, Ray T. Chen, David Z. Pan:
L2ight: Enabling On-Chip Learning for Optical Neural Networks via Efficient in-situ Subspace Optimization. NeurIPS 2021: 8649-8661 - [i32]Zixuan Jiang, Jiaqi Gu, Mingjie Liu, Keren Zhu, David Z. Pan:
Optimizer Fusion: Efficient Training with Better Locality and Parallelism. CoRR abs/2104.00237 (2021) - [i31]Hanrui Wang, Yongshan Ding, Jiaqi Gu, Yujun Lin, David Z. Pan, Frederic T. Chong, Song Han:
QuantumNAS: Noise-Adaptive Search for Robust Quantum Circuits. CoRR abs/2107.10845 (2021) - [i30]Jiaqi Gu, Hanqing Zhu, Chenghao Feng, Mingjie Liu, Zixuan Jiang, Ray T. Chen, David Z. Pan:
Towards Memory-Efficient Neural Networks via Multi-Level in situ Generation. CoRR abs/2108.11430 (2021) - [i29]Zixuan Jiang, Ebrahim M. Songhori, Shen Wang, Anna Goldie, Azalia Mirhoseini, Joe W. J. Jiang, Young-Joon Lee, David Z. Pan:
Delving into Macro Placement with Reinforcement Learning. CoRR abs/2109.02587 (2021) - [i28]Ahmet Faruk Budak, Prateek Bhansali, Bo Liu, Nan Sun, David Z. Pan, Chandramouli V. Kashyap:
DNN-Opt: An RL Inspired Optimization for Analog Circuit Sizing using Deep Neural Networks. CoRR abs/2110.00211 (2021) - [i27]Zixuan Jiang, Jiaqi Gu, David Z. Pan:
A New Acceleration Paradigm for Discrete CosineTransform and Other Fourier-Related Transforms. CoRR abs/2110.01172 (2021) - [i26]Hanrui Wang, Jiaqi Gu, Yongshan Ding, Zirui Li, Frederic T. Chong, David Z. Pan, Song Han:
RoQNN: Noise-Aware Training for Robust Quantum Neural Networks. CoRR abs/2110.11331 (2021) - [i25]Jiaqi Gu, Hanqing Zhu, Chenghao Feng, Zixuan Jiang, Ray T. Chen, David Z. Pan:
L2ight: Enabling On-Chip Learning for Optical Neural Networks via Efficient in-situ Subspace Optimization. CoRR abs/2110.14807 (2021) - [i24]Jiaqi Gu, Hyoukjun Kwon, Dilin Wang, Wei Ye, Meng Li, Yu-Hsin Chen, Liangzhen Lai, Vikas Chandra, David Z. Pan:
Multi-Scale High-Resolution Vision Transformer for Semantic Segmentation. CoRR abs/2111.01236 (2021) - [i23]Chenghao Feng, Jiaqi Gu, Hanqing Zhu, Zhoufeng Ying, Zheng Zhao, David Z. Pan, Ray T. Chen:
Silicon photonic subspace neural chip for hardware-efficient deep learning. CoRR abs/2111.06705 (2021) - [i22]Hanqing Zhu, Jiaqi Gu, Chenghao Feng, Mingjie Liu, Zixuan Jiang, Ray T. Chen, David Z. Pan:
ELight: Enabling Efficient Photonic In-Memory Neurocomputing with Life Enhancement. CoRR abs/2112.08512 (2021) - [i21]Jiaqi Gu, Hanqing Zhu, Chenghao Feng, Zixuan Jiang, Mingjie Liu, Shuhan Zhang, Ray T. Chen, David Z. Pan:
ADEPT: Automatic Differentiable DEsign of Photonic Tensor Cores. CoRR abs/2112.08703 (2021) - 2020
- [j91]Jing Chen, Mohamed Baker Alawieh, Yibo Lin, Maolin Zhang, Jun Zhang, Yufeng Guo, David Z. Pan:
Powernet: SOI Lateral Power Device Breakdown Prediction With Deep Neural Networks. IEEE Access 8: 25372-25382 (2020) - [j90]David Z. Pan:
Report on the 38th ACM/IEEE International Conference on Computer-Aided Design (ICCAD 2019). IEEE Des. Test 37(2): 121-122 (2020) - [j89]Wenda Zhao, Shaolan Li, Biying Xu, Xiangxing Yang, Xiyuan Tang, Linxiao Shen, Nanshu Lu, David Z. Pan, Nan Sun:
A 0.025-mm2 0.8-V 78.5-dB SNDR VCO-Based Sensor Readout Circuit in a Hybrid PLL- ΔΣ M Structure. IEEE J. Solid State Circuits 55(3): 666-679 (2020) - [j88]Xiyuan Tang, Linxiao Shen, Begum Kasap, Xiangxing Yang, Wei Shi, Abhishek Mukherjee, David Z. Pan, Nan Sun:
An Energy-Efficient Comparator With Dynamic Floating Inverter Amplifier. IEEE J. Solid State Circuits 55(4): 1011-1022 (2020) - [j87]Shaolan Li, David Z. Pan, Nan Sun:
An OTA-Less Second-Order VCO-Based CT $\Delta\Sigma$ Modulator Using an Inherent Passive Integrator and Capacitive Feedback. IEEE J. Solid State Circuits 55(5): 1337-1350 (2020) - [j86]Xiyuan Tang, Shaolan Li, Xiangxing Yang, Linxiao Shen, Wenda Zhao, Randall P. Williams, Jiaxin Liu, Zhichao Tan, Neal A. Hall, David Z. Pan, Nan Sun:
An Energy-Efficient Time-Domain Incremental Zoom Capacitance-to-Digital Converter. IEEE J. Solid State Circuits 55(11): 3064-3075 (2020) - [j85]Xiyuan Tang, Xiangxing Yang, Wenda Zhao, Chen-Kai Hsu, Jiaxin Liu, Linxiao Shen, Abhishek Mukherjee, Wei Shi, Shaolan Li, David Z. Pan, Nan Sun:
A 13.5-ENOB, 107-μW Noise-Shaping SAR ADC With PVT-Robust Closed-Loop Dynamic Amplifier. IEEE J. Solid State Circuits 55(12): 3248-3259 (2020) - [j84]Ying Chen, Yibo Lin, Tianyang Gai, Yajuan Su, Yayi Wei, David Z. Pan:
Semisupervised Hotspot Detection With Self-Paced Multitask Learning. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(7): 1511-1523 (2020) - [j83]Grace Li Zhang, Bing Li, Meng Li, Bei Yu, David Z. Pan, Michaela Brunner, Georg Sigl, Ulf Schlichtmann:
TimingCamouflage+: Netlist Security Enhancement With Unconventional Timing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(12): 4482-4495 (2020) - [j82]Yibo Lin, Wuxi Li, Jiaqi Gu, Haoxing Ren, Brucek Khailany, David Z. Pan:
ABCDPlace: Accelerated Batch-Based Concurrent Detailed Placement on Multithreaded CPUs and GPUs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(12): 5083-5096 (2020) - [j81]Taehyun Kwon, Muhammad Imran, David Z. Pan, Joon-Sung Yang:
Virtual-Tile-Based Flip-Flop Alignment Methodology for Clock Network Power Optimization. IEEE Trans. Very Large Scale Integr. Syst. 28(5): 1256-1268 (2020) - [c226]Mohamed Baker Alawieh, Wuxi Li, Yibo Lin, Love Singhal, Mahesh A. Iyer, David Z. Pan:
High-Definition Routing Congestion Prediction for Large-Scale FPGAs. ASP-DAC 2020: 26-31 - [c225]Mingjie Liu, Wuxi Li, Keren Zhu, Biying Xu, Yibo Lin, Linxiao Shen, Xiyuan Tang, Nan Sun, David Z. Pan:
S3DET: Detecting System Symmetry Constraints for Analog Circuits with Graph Similarity. ASP-DAC 2020: 193-198 - [c224]Jiaqi Gu, Zheng Zhao, Chenghao Feng, Mingjie Liu, Ray T. Chen, David Z. Pan:
Towards Area-Efficient Optical Neural Networks: An FFT-based Architecture. ASP-DAC 2020: 476-481 - [c223]Mohamed Baker Alawieh, Duane S. Boning, David Z. Pan:
Wafer Map Defect Patterns Classification using Deep Selective Learning. DAC 2020: 1-6 - [c222]Jiaqi Gu, Zheng Zhao, Chenghao Feng, Wuxi Li, Ray T. Chen, David Z. Pan:
FLOPS: EFficient On-Chip Learning for OPtical Neural Networks Through Stochastic Zeroth-Order Optimization. DAC 2020: 1-6 - [c221]Navid Khoshavi, Arman Roohi, Connor Broyles, Saman Sargolzaei, Yu Bi, David Z. Pan:
SHIELDeNN: Online Accelerated Framework for Fault-Tolerant Deep Neural Network Architectures. DAC 2020: 1-6 - [c220]Mingjie Liu, Keren Zhu, Xiyuan Tang, Biying Xu, Wei Shi, Nan Sun, David Z. Pan:
Closing the Design Loop: Bayesian Optimization Assisted Hierarchical Analog Layout Synthesis. DAC 2020: 1-6 - [c219]Mingjie Liu, Keren Zhu, Jiaqi Gu, Linxiao Shen, Xiyuan Tang, Nan Sun, David Z. Pan:
Towards Decrypting the Art of Analog Layout: Placement Quality Prediction via Transfer Learning. DATE 2020: 496-501 - [c218]Jiaqi Gu, Zheng Zhao, Chenghao Feng, Hanqing Zhu, Ray T. Chen, David Z. Pan:
ROQ: A Noise-Aware Quantization Scheme Towards Robust Optical Neural Networks with Low-bit Controls. DATE 2020: 1586-1589 - [c217]Zixuan Jiang, Keren Zhu, Mingjie Liu, Jiaqi Gu, David Z. Pan:
An Efficient Training Framework for Reversible Neural Architectures. ECCV (27) 2020: 275-289 - [c216]Rachel Selina Rajarathnam, Yibo Lin, Yier Jin, David Z. Pan:
ReGDS: A Reverse Engineering Framework from GDSII to Gate-level Netlist. HOST 2020: 154-163 - [c215]Mohamed Baker Alawieh, Wei Ye, David Z. Pan:
Re-examining VLSI Manufacturing and Yield through the Lens of Deep Learning : (Invited Talk). ICCAD 2020: 12:1-12:8 - [c214]Hao Chen, Keren Zhu, Mingjie Liu, Xiyuan Tang, Nan Sun, David Z. Pan:
Toward Silicon-Proven Detailed Routing for Analog and Mixed-Signal Circuits. ICCAD 2020: 18:1-18:8 - [c213]Keren Zhu, Hao Chen, Mingjie Liu, Xiyuan Tang, Nan Sun, David Z. Pan:
Effective Analog/Mixed-Signal Circuit Placement Considering System Signal Flow. ICCAD 2020: 133:1-133:9 - [c212]Jiaqi Gu, Zixuan Jiang, Yibo Lin, David Z. Pan:
DREAMPlace 3.0: Multi-Electrostatics Based Robust VLSI Placement with Region Constraints. ICCAD 2020: 143:1-143:9 - [c211]Wei Ye, Mohamed Baker Alawieh, Yuki Watanabe, Shigeki Nojima, Yibo Lin, David Z. Pan:
TEMPO: Fast Mask Topography Effect Modeling with Deep Learning. ISPD 2020: 127-134 - [c210]Xiyuan Tang, Xiangxing Yang, Wenda Zhao, Chen-Kai Hsu, Jiaxin Liu, Linxiao Shen, Abhishek Mukherjee, Wei Shi, David Z. Pan, Nan Sun:
9.5 A 13.5b-ENOB Second-Order Noise-Shaping SAR with PVT-Robust Closed-Loop Dynamic Amplifier. ISSCC 2020: 162-164 - [c209]Raviv Gal, David Z. Pan, Haoxing Ren, Manish Pandey, Marilyn Wolf, Avi Ziv:
ML for CAD - Where is the Treasure Hiding? MLCAD 2020: 137 - [c208]Keren Zhu, Mingjie Liu, Hao Chen, Zheng Zhao, David Z. Pan:
Exploring Logic Optimizations with Reinforcement Learning and Graph Convolutional Network. MLCAD 2020: 145-150 - [i20]Grace Li Zhang, Bing Li, Meng Li, Bei Yu, David Z. Pan, Michaela Brunner, Georg Sigl, Ulf Schlichtmann:
TimingCamouflage+: Netlist Security Enhancement with Unconventional Timing (with Appendix). CoRR abs/2003.00862 (2020) - [i19]Shubham Rai, Walter Lau Neto, Yukio Miyasaka, Xinpei Zhang, Mingfei Yu, Qingyang Yi, Masahiro Fujita, Guilherme B. Manske, Matheus F. Pontes, Leomar S. da Rosa Jr., Marilton S. de Aguiar, Paulo F. Butzen, Po-Chun Chien, Yu-Shan Huang, Hoa-Ren Wang, Jie-Hong R. Jiang, Jiaqi Gu, Zheng Zhao, Zixuan Jiang, David Z. Pan, Brunno A. Abreu, Isac de Souza Campos, Augusto Andre Souza Berndt, Cristina Meinhardt, Jônata Tyska Carvalho, Mateus Grellert, Sergio Bampi, Aditya Lohana, Akash Kumar, Wei Zeng, Azadeh Davoodi, Rasit Onur Topaloglu, Yuan Zhou, Jordan Dotzel, Yichi Zhang, Hanyu Wang, Zhiru Zhang, Valerio Tenace, Pierre-Emmanuel Gaillardon, Alan Mishchenko, Satrajit Chatterjee:
Logic Synthesis Meets Machine Learning: Trading Exactness for Generalization. CoRR abs/2012.02530 (2020) - [i18]Jiaqi Gu, Chenghao Feng, Zheng Zhao, Zhoufeng Ying, Ray T. Chen, David Z. Pan:
Efficient On-Chip Learning for Optical Neural Networks Through Power-Aware Sparse Zeroth-Order Optimization. CoRR abs/2012.11148 (2020)
2010 – 2019
- 2019
- [j80]Derong Liu, Bei Yu, Vinicius S. Livramento, Salim Chowdhury, Duo Ding, Huy Vo, Akshay Sharma, David Z. Pan:
Synergistic Topology Generation and Route Synthesis for On-Chip Performance-Critical Signal Groups. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(6): 1147-1160 (2019) - [j79]Meng Li, Kaveh Shamsi, Travis Meade, Zheng Zhao, Bei Yu, Yier Jin, David Z. Pan:
Provably Secure Camouflaging Strategy for IC Protection. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(8): 1399-1412 (2019) - [j78]Meng Li, Bei Yu, Yibo Lin, Xiaoqing Xu, Wuxi Li, David Z. Pan:
A Practical Split Manufacturing Framework for Trojan Prevention via Simultaneous Wire Lifting and Cell Insertion. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(9): 1585-1598 (2019) - [j77]Yibo Lin, Meng Li, Yuki Watanabe, Taiki Kimura, Tetsuaki Matsunawa, Shigeki Nojima, David Z. Pan:
Data Efficient Lithography Modeling With Transfer Learning and Active Data Selection. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(10): 1900-1913 (2019) - [j76]Wuxi Li, David Z. Pan:
A New Paradigm for FPGA Placement Without Explicit Packing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(11): 2113-2126 (2019) - [j75]Kaveh Shamsi, Travis Meade, Meng Li, David Z. Pan, Yier Jin:
On the Approximation Resiliency of Logic Locking and IC Camouflaging Schemes. IEEE Trans. Inf. Forensics Secur. 14(2): 347-359 (2019) - [j74]Kaveh Shamsi, Meng Li, Kenneth Plaks, Saverio Fazzari, David Z. Pan, Yier Jin:
IP Protection and Supply Chain Security through Logic Obfuscation: A Systematic Overview. ACM Trans. Design Autom. Electr. Syst. 24(6): 65:1-65:36 (2019) - [c207]Wei Li, Yuzhe Ma, Qi Sun, Yibo Lin, Iris Hui-Ru Jiang, Bei Yu, David Z. Pan:
OpenMPL: An Open Source Layout Decomposer: Invited Paper. ASICON 2019: 1-4 - [c206]Wei Ye, Mohamed Baker Alawieh, Yibo Lin, David Z. Pan:
Tackling signal electromigration with learning-based detection and multistage mitigation. ASP-DAC 2019: 167-172 - [c205]Mohamed Baker Alawieh, Xiyuan Tang, David Z. Pan:
S2-PM: semi-supervised learning for efficient performance modeling of analog and mixed signal circuits. ASP-DAC 2019: 268-273 - [c204]Wei Ye, Yibo Lin, Meng Li, Qiang Liu, David Z. Pan:
LithoROC: lithography hotspot detection with explicit ROC optimization. ASP-DAC 2019: 292-298 - [c203]Ying Chen, Yibo Lin, Tianyang Gai, Yajuan Su, Yayi Wei, David Z. Pan:
Semi-supervised hotspot detection with self-paced multi-task learning. ASP-DAC 2019: 420-425 - [c202]Shounak Dhar, Love Singhal, Mahesh A. Iyer, David Z. Pan:
A shape-driven spreading algorithm using linear programming for global placement. ASP-DAC 2019: 563-568 - [c201]Zheng Zhao, Derong Liu, Meng Li, Zhoufeng Ying, Lu Zhang, Biying Xu, Bei Yu, Ray T. Chen, David Z. Pan:
Hardware-software co-design of slimmed optical neural networks. ASP-DAC 2019: 705-710 - [c200]Shaolan Li, Biying Xu, David Z. Pan, Nan Sun:
A 60-fJ/step 11-ENOB VCO-based CTDSM Synthesized from Digital Standard Cell Library. CICC 2019: 1-4 - [c199]Shaolan Li, Wenda Zhao, Biying Xu, Xiangxing Yang, Xiyuan Tang, Linxiao Shen, Nanshu Lu, David Z. Pan, Nan Sun:
A 0.025-mm2 0.8-V 78.5dB-SNDR VCO-Based Sensor Readout Circuit in a Hybrid PLL-ΔΣM Structure. CICC 2019: 1-3 - [c198]Mohamed Baker Alawieh, Sinead A. Williamson, David Z. Pan:
Rethinking Sparsity in Performance Modeling for Analog and Mixed Circuits using Spike and Slab Models. DAC 2019: 65 - [c197]Biying Xu, Yibo Lin, Xiyuan Tang, Shaolan Li, Linxiao Shen, Nan Sun, David Z. Pan:
WellGAN: Generative-Adversarial-Network-Guided Well Generation for Analog/Mixed-Signal Circuit Layout. DAC 2019: 66 - [c196]Wei Ye, Mohamed Baker Alawieh, Yibo Lin, David Z. Pan:
LithoGAN: End-to-End Lithography Modeling with Generative Adversarial Networks. DAC 2019: 107 - [c195]Yibo Lin, Shounak Dhar, Wuxi Li, Haoxing Ren, Brucek Khailany, David Z. Pan:
DREAMPlace: Deep Learning Toolkit-Enabled GPU Acceleration for Modern VLSI Placement. DAC 2019: 117 - [c194]Mohamed Baker Alawieh, Yibo Lin, Zaiwei Zhang, Meng Li, Qixing Huang, David Z. Pan:
GAN-SRAF: Sub-Resolution Assist Feature Generation Using Conditional Generative Adversarial Networks. DAC 2019: 149 - [c193]Wei Ye, Mohamed Baker Alawieh, Meng Li, Yibo Lin, David Z. Pan:
Litho-GPA: Gaussian Process Assurance for Lithography Hotspot Detection. DATE 2019: 54-59 - [c192]Kaveh Shamsi, Meng Li, David Z. Pan, Yier Jin:
KC2: Key-Condition Crunching for Fast Sequential Circuit Deobfuscation. DATE 2019: 534-539 - [c191]Zheng Zhao, Derong Liu, Zhoufeng Ying, Biying Xu, Chenghao Feng, Ray T. Chen, David Z. Pan:
Exploiting Wavelength Division Multiplexing for Optical Logic Synthesis. DATE 2019: 1567-1570 - [c190]Wuxi Li, Mehrdad E. Dehkordi, Stephen Yang, David Z. Pan:
Simultaneous Placement and Clock Tree Construction for Modern FPGAs. FPGA 2019: 132-141 - [c189]Shounak Dhar, Love Singhal, Mahesh A. Iyer, David Z. Pan:
FPGA Accelerated FPGA Placement. FPL 2019: 404-410 - [c188]Kaveh Shamsi, David Z. Pan, Yier Jin:
On the Impossibility of Approximation-Resilient Circuit Locking. HOST 2019: 161-170 - [c187]Shounak Dhar, Love Singhal, Mahesh A. Iyer, David Z. Pan:
FPGA-Accelerated Spreading for Global Placement. HPEC 2019: 1-7 - [c186]ChengYue Gong, Zixuan Jiang, Dilin Wang, Yibo Lin, Qiang Liu, David Z. Pan:
Mixed Precision Neural Architecture Search for Energy Efficient Deep Learning. ICCAD 2019: 1-7 - [c185]Wuxi Li, Yibo Lin, David Z. Pan:
elfPlace: Electrostatics-based Placement for Large-Scale Heterogeneous FPGAs. ICCAD 2019: 1-8 - [c184]Kaveh Shamsi, David Z. Pan, Yier Jin:
IcySAT: Improved SAT-based Attacks on Cyclic Locked Circuits. ICCAD 2019: 1-7 - [c183]Biying Xu, Keren Zhu, Mingjie Liu, Yibo Lin, Shaolan Li, Xiyuan Tang, Nan Sun, David Z. Pan:
MAGICAL: Toward Fully Automated Analog IC Layout Leveraging Human and Machine Intelligence: Invited Paper. ICCAD 2019: 1-8 - [c182]Zheng Zhao, Jiaqi Gu, Zhoufeng Ying, Chenghao Feng, Ray T. Chen, David Z. Pan:
Design Technology for Scalable and Robust Photonic Integrated Circuits: Invited Paper. ICCAD 2019: 1-7 - [c181]Keren Zhu, Mingjie Liu, Yibo Lin, Biying Xu, Shaolan Li, Xiyuan Tang, Nan Sun, David Z. Pan:
GeniusRoute: A New Analog Routing Paradigm Using Generative Neural Network Guidance. ICCAD 2019: 1-8 - [c180]Biying Xu, Shaolan Li, Chak-Wa Pui, Derong Liu, Linxiao Shen, Yibo Lin, Nan Sun, David Z. Pan:
Device Layer-Aware Analytical Placement for Analog Circuits. ISPD 2019: 19-26 - [e3]David Z. Pan:
Proceedings of the International Conference on Computer-Aided Design, ICCAD 2019, Westminster, CO, USA, November 4-7, 2019. ACM 2019, ISBN 9781728123509 [contents] - 2018
- [j73]Sri Parameswaran, R. Iris Bahar, David Z. Pan:
Conference Reports: Report on the 2017 International Conference on Computer-Aided Design (ICCAD). IEEE Des. Test 35(2): 101-102 (2018) - [j72]Shaolan Li, Bo Qiao, Miguel Gandara, David Z. Pan, Nan Sun:
A 13-ENOB Second-Order Noise-Shaping SAR ADC Realizing Optimized NTF Zeros Using the Error-Feedback Structure. IEEE J. Solid State Circuits 53(12): 3484-3496 (2018) - [j71]Derong Liu, Bei Yu, Salim Chowdhury, David Z. Pan:
TILA-S: Timing-Driven Incremental Layer Assignment Avoiding Slew Violations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(1): 231-244 (2018) - [j70]Taehee Lee, David Z. Pan, Joon-Sung Yang:
Clock Network Optimization With Multibit Flip-Flop Generation Considering Multicorner Multimode Timing Constraint. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(1): 245-256 (2018) - [j69]Hengliang Zhu, Feng Hu, Hao Zhou, David Z. Pan, Dian Zhou, Xuan Zeng:
Interlayer Cooling Network Design for High-Performance 3D ICs Using Channel Patterning and Pruning. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(4): 770-781 (2018) - [j68]Wuxi Li, Shounak Dhar, David Z. Pan:
UTPlaceF: A Routability-Driven FPGA Placer With Physical and Congestion Aware Packing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(4): 869-882 (2018) - [j67]Xiaoqing Xu, Yibo Lin, Meng Li, Tetsuaki Matsunawa, Shigeki Nojima, Chikaaki Kodama, Toshiya Kotani, David Z. Pan:
Subresolution Assist Feature Generation With Supervised Data Learning. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(6): 1225-1236 (2018) - [j66]Yibo Lin, Bei Yu, Xiaoqing Xu, Jhih-Rong Gao, Natarajan Viswanathan, Wen-Hao Liu, Zhuo Li, Charles J. Alpert, David Z. Pan:
MrDP: Multiple-Row Detailed Placement of Heterogeneous-Sized Cells for Advanced Nodes. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(6): 1237-1250 (2018) - [j65]Yibo Lin, Bei Yu, Meng Li, David Z. Pan:
Layout Synthesis for Topological Quantum Circuits With 1-D and 2-D Architectures. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(8): 1574-1587 (2018) - [j64]Wuxi Li, Yibo Lin, Meng Li, Shounak Dhar, David Z. Pan:
UTPlaceF 2.0: A High-Performance Clock-Aware FPGA Placement Engine. ACM Trans. Design Autom. Electr. Syst. 23(4): 42:1-42:23 (2018) - [j63]Hao Zhou, Hengliang Zhu, Tao Cui, David Z. Pan, Dian Zhou, Xuan Zeng:
Thermal Stress and Reliability Analysis of TSV-Based 3-D ICs With a Novel Adaptive Strategy Finite Element Method. IEEE Trans. Very Large Scale Integr. Syst. 26(7): 1312-1325 (2018) - [j62]Ye Zhang, Wenlong Lyu, Wai-Shing Luk, Fan Yang, Hai Zhou, Dian Zhou, David Z. Pan, Xuan Zeng:
Cut Redistribution and Insertion for Advanced 1-D Layout Design via Network Flow Optimization. IEEE Trans. Very Large Scale Integr. Syst. 26(9): 1613-1626 (2018) - [j61]Xingquan Li, Bei Yu, Jiaojiao Ou, Jianli Chen, David Z. Pan, Wenxing Zhu:
Graph-Based Redundant Via Insertion and Guiding Template Assignment for DSA-MP. IEEE Trans. Very Large Scale Integr. Syst. 26(11): 2504-2517 (2018) - [c179]Che-Lun Hsu, Shaofeng Guo, Yibo Lin, Xiaoqing Xu, Meng Li, Runsheng Wang, Ru Huang, David Z. Pan:
Layout-dependent aging mitigation for critical path timing. ASP-DAC 2018: 153-158 - [c178]Meng Li, Bei Yu, Yibo Lin, Xiaoqing Xu, Wuxi Li, David Z. Pan:
A practical split manufacturing framework for Trojan prevention via simultaneous wire lifting and cell insertion. ASP-DAC 2018: 265-270 - [c177]Zheng Zhao, Zheng Wang, Zhoufeng Ying, Shounak Dhar, Ray T. Chen, David Z. Pan:
Logic synthesis for energy-efficient photonic integrated circuits. ASP-DAC 2018: 355-360 - [c176]Derong Liu, Zheng Zhao, Zheng Wang, Zhoufeng Ying, Ray T. Chen, David Z. Pan:
OPERON: optical-electrical power-efficient route synthesis for on-chip signals. DAC 2018: 75:1-75:6 - [c175]Grace Li Zhang, Bing Li, Bei Yu, David Z. Pan, Ulf Schlichtmann:
TimingCamouflage: Improving circuit security against counterfeiting by unconventional timing. DATE 2018: 91-96 - [c174]Kaveh Shamsi, Meng Li, David Z. Pan, Yier Jin:
Cross-Lock: Dense Layout-Level Interconnect Locking using Cross-bar Architectures. ACM Great Lakes Symposium on VLSI 2018: 147-152 - [c173]Shounak Dhar, David Z. Pan:
GDP: GPU accelerated Detailed Placement. HPEC 2018: 1-7 - [c172]Wei Ye, Meng Li, Kai Zhong, Bei Yu, David Z. Pan:
Power Grid Reduction by Sparse Convex Optimization. ISPD 2018: 60-67 - [c171]Yibo Lin, Yuki Watanabe, Taiki Kimura, Tetsuaki Matsunawa, Shigeki Nojima, Meng Li, David Z. Pan:
Data Efficient Lithography Modeling with Residual Neural Networks and Transfer Learning. ISPD 2018: 82-89 - [c170]Biying Xu, Bülent Basaran, Ming Su, David Z. Pan:
Analog Placement Constraint Extraction and Exploration with the Application to Layout Retargeting. ISPD 2018: 98-105 - [c169]Meng Li, Kaveh Shamsi, Yier Jin, David Z. Pan:
TimingSAT: Decamouflaging Timing-based Logic Obfuscation. ITC 2018: 1-10 - [c168]Yibo Lin, Mohamed Baker Alawieh, Wei Ye, David Z. Pan:
Machine Learning for Yield Learning and Optimization. ITC 2018: 1-10 - [c167]David Z. Pan:
Machine learning for IC design and technology co-optimization in extreme scaling. VLSI-DAT 2018: 1 - [i17]Yibo Lin, Meng Li, Yuki Watanabe, Taiki Kimura, Tetsuaki Matsunawa, Shigeki Nojima, David Z. Pan:
Data Efficient Lithography Modeling with Transfer Learning and Active Data Selection. CoRR abs/1807.03257 (2018) - [i16]Qi Sun, Yibo Lin, Iris Hui-Ru Jiang, Bei Yu, David Z. Pan:
OpenMPL: An Open Source Layout Decomposer. CoRR abs/1809.07554 (2018) - 2017
- [j60]Yibo Lin, Bei Yu, Yi Zou, Zhuo Li, Charles J. Alpert, David Z. Pan:
Stitch aware detailed placement for multiple E-beam lithography. Integr. 58: 47-54 (2017) - [j59]Xiaoqing Xu, David Z. Pan:
Toward Unidirectional Routing Closure in Advanced Technology Nodes. IPSJ Trans. Syst. LSI Des. Methodol. 10: 2-12 (2017) - [j58]Xiaoqing Xu, Yibo Lin, Meng Li, Jiaojiao Ou, Brian Cline, David Z. Pan:
Redundant Local-Loop Insertion for Unidirectional Routing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36(7): 1113-1125 (2017) - [j57]Vinicius S. Livramento, Derong Liu, Salim Chowdhury, Bei Yu, Xiaoqing Xu, David Z. Pan, José Luís Almada Güntzel, Luiz C. V. dos Santos:
Incremental Layer Assignment Driven by an External Signoff Timing Engine. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36(7): 1126-1139 (2017) - [j56]Yibo Lin, Bei Yu, Biying Xu, David Z. Pan:
Triple Patterning Aware Detailed Placement Toward Zero Cross-Row Middle-of-Line Conflict. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36(7): 1140-1152 (2017) - [j55]Yibo Lin, Bei Yu, David Z. Pan:
High Performance Dummy Fill Insertion With Coupling and Uniformity Constraints. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36(9): 1532-1544 (2017) - [j54]Derong Liu, Bei Yu, Salim Chowdhury, David Z. Pan:
Incremental Layer Assignment for Timing Optimization. ACM Trans. Design Autom. Electr. Syst. 22(4): 75:1-75:25 (2017) - [j53]Yunfeng Yang, Wai-Shing Luk, Hai Zhou, David Z. Pan, Dian Zhou, Changhao Yan, Xuan Zeng:
An Effective Layout Decomposition Method for DSA with Multiple Patterning in Contact-Hole Generation. ACM Trans. Design Autom. Electr. Syst. 23(1): 11:1-11:27 (2017) - [c166]Zheng Zhao, Zheng Wang, Zhoufeng Ying, Shounak Dhar, Ray T. Chen, David Z. Pan:
Optical computing on silicon-on-insulator-based photonic integrated circuits. ASICON 2017: 472-475 - [c165]Biying Xu, Shaolan Li, Nan Sun, David Z. Pan:
A Scaling Compatible, Synthesis Friendly VCO-based Delta-sigma ADC Design and Synthesis Methodology. DAC 2017: 12:1-12:6 - [c164]Meng Li, Liangzhen Lai, Vikas Chandra, David Z. Pan:
Cross-level Monte Carlo Framework for System Vulnerability Evaluation against Fault Attack. DAC 2017: 17:1-17:6 - [c163]Derong Liu, Vinicius S. Livramento, Salim Chowdhury, Duo Ding, Huy Vo, Akshay Sharma, David Z. Pan:
Streak: Synergistic Topology Generation and Route Synthesis for On-Chip Performance-Critical Signal Groups. DAC 2017: 18:1-18:6 - [c162]Xiaoqing Xu, Yibo Lin, Vinicius S. Livramento, David Z. Pan:
Concurrent Pin Access Optimization for Unidirectional Routing. DAC 2017: 20:1-20:6 - [c161]Kaveh Shamsi, Meng Li, Travis Meade, Zheng Zhao, David Z. Pan, Yier Jin:
Cyclic Obfuscation for Creating SAT-Unresolvable Circuits. ACM Great Lakes Symposium on VLSI 2017: 173-178 - [c160]Kaveh Shamsi, Meng Li, Travis Meade, Zheng Zhao, David Z. Pan, Yier Jin:
Circuit Obfuscation and Oracle-guided Attacks: Who can Prevail? ACM Great Lakes Symposium on VLSI 2017: 357-362 - [c159]Kaveh Shamsi, Meng Li, Travis Meade, Zheng Zhao, David Z. Pan, Yier Jin:
AppSAT: Approximately deobfuscating integrated circuits. HOST 2017: 95-100 - [c158]Wuxi Li, Meng Li, Jiajun Wang, David Z. Pan:
UTPlaceF 3.0: A parallelization framework for modern FPGA global placement: (Invited paper). ICCAD 2017: 922-928 - [c157]Jiaojiao Ou, Xiaoqing Xu, Brian Cline, Greg Yeric, David Z. Pan:
DTCO for DSA-MP Hybrid Lithography with Double-BCP Materials in Sub-7nm Node. ICCD 2017: 403-410 - [c156]Yibo Lin, Peter Debacker, Darko Trivkovic, Ryoung-Han Kim, Praveen Raghavan, David Z. Pan:
Patterning Aware Design Optimization of Selective Etching in N5 and Beyond. ICCD 2017: 415-418 - [c155]Travis Meade, Zheng Zhao, Shaojie Zhang, David Z. Pan, Yier Jin:
Revisit sequential logic obfuscation: Attacks and defenses. ISCAS 2017: 1-4 - [c154]Wei Ye, Yibo Lin, Xiaoqing Xu, Wuxi Li, Yiwei Fu, Yongsheng Sun, Canhui Zhan, David Z. Pan:
Placement mitigation techniques for power grid electromigration. ISLPED 2017: 1-6 - [c153]Biying Xu, Shaolan Li, Xiaoqing Xu, Nan Sun, David Z. Pan:
Hierarchical and Analytical Placement Techniques for High-Performance Analog Circuits. ISPD 2017: 55-62 - [c152]Jiaojiao Ou, Bei Yu, Xiaoqing Xu, Joydeep Mitra, Yibo Lin, David Z. Pan:
DSAR: DSA aware Routing with Simultaneous DSA Guiding Pattern and Double Patterning Assignment. ISPD 2017: 91-98 - [c151]Shounak Dhar, Mahesh A. Iyer, Saurabh N. Adya, Love Singhal, Nikolay Rubanov, David Z. Pan:
An Effective Timing-Driven Detailed Placement Algorithm for FPGAs. ISPD 2017: 151-157 - [i15]Meng Li, Liangzhen Lai, Naveen Suda, Vikas Chandra, David Z. Pan:
PrivyNet: A Flexible Framework for Privacy-Preserving Deep Neural Network Training with A Fine-Grained Privacy Control. CoRR abs/1709.06161 (2017) - 2016
- [j52]Bei Yu, Xiaoqing Xu, Subhendu Roy, Yibo Lin, Jiaojiao Ou, David Z. Pan:
Design for manufacturability and reliability in extreme-scaling VLSI. Sci. China Inf. Sci. 59(6): 061406:1-061406:23 (2016) - [j51]Subhendu Roy, Mihir R. Choudhury, Ruchir Puri, David Z. Pan:
Polynomial Time Algorithm for Area and Power Efficient Adder Synthesis in High-Performance Designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(5): 820-831 (2016) - [j50]Yunfeng Yang, Wai-Shing Luk, David Z. Pan, Hai Zhou, Changhao Yan, Dian Zhou, Xuan Zeng:
Layout Decomposition Co-Optimization for Hybrid E-Beam and Multiple Patterning Lithography. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(9): 1532-1545 (2016) - [j49]Subhendu Roy, Derong Liu, Jagmohan Singh, Junhyung Um, David Z. Pan:
OSFA: A New Paradigm of Aging Aware Gate-Sizing for Power/Performance Optimizations Under Multiple Operating Conditions. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(10): 1618-1629 (2016) - [j48]Xiaoqing Xu, Bei Yu, Jhih-Rong Gao, Che-Lun Hsu, David Z. Pan:
PARR: Pin-Access Planning and Regular Routing for Self-Aligned Double Patterning. ACM Trans. Design Autom. Electr. Syst. 21(3): 42:1-42:21 (2016) - [j47]Bei Yu, Kun Yuan, Jhih-Rong Gao, Shiyan Hu, David Z. Pan:
EBL Overlapping Aware Stencil Planning for MCC System. ACM Trans. Design Autom. Electr. Syst. 21(3): 43:1-43:24 (2016) - [c150]Yibo Lin, Bei Yu, Yi Zou, Zhuo Li, Charles J. Alpert, David Z. Pan:
Stitch aware detailed placement for multiple e-beam lithography. ASP-DAC 2016: 186-191 - [c149]Tetsuaki Matsunawa, Bei Yu, David Z. Pan:
Laplacian eigenmaps and bayesian clustering based layout pattern sampling and its applications to hotspot detection and OPC. ASP-DAC 2016: 679-684 - [c148]Derong Liu, Bei Yu, Salim Chowdhury, David Z. Pan:
Incremental layer assignment for critical path timing. DAC 2016: 85:1-85:6 - [c147]Meng Li, Jin Miao, Kai Zhong, David Z. Pan:
Practical public PUF enabled by solving max-flow problem on chip. DAC 2016: 164:1-164:6 - [c146]Yibo Lin, Bei Yu, Xiaoqing Xu, Jhih-Rong Gao, Natarajan Viswanathan, Wen-Hao Liu, Zhuo Li, Charles J. Alpert, David Z. Pan:
MrDP: multiple-row detailed placement of heterogeneous-sized cells for advanced nodes. ICCAD 2016: 7 - [c145]Shounak Dhar, Saurabh N. Adya, Love Singhal, Mahesh A. Iyer, David Z. Pan:
Detailed placement for modern FPGAs using 2D dynamic programming. ICCAD 2016: 9 - [c144]Meng Li, Kaveh Shamsi, Travis Meade, Zheng Zhao, Bei Yu, Yier Jin, David Z. Pan:
Provably secure camouflaging strategy for IC protection. ICCAD 2016: 28 - [c143]Wuxi Li, Shounak Dhar, David Z. Pan:
UTPlaceF: a routability-driven FPGA placer with physical and congestion aware packing. ICCAD 2016: 66 - [c142]Yudong Tao, Changhao Yan, Yibo Lin, Sheng-Guo Wang, David Z. Pan, Xuan Zeng:
A novel unified dummy fill insertion framework with SQP-based optimization method. ICCAD 2016: 88 - [c141]Jiaojiao Ou, Bei Yu, David Z. Pan:
Concurrent Guiding Template Assignment and Redundant via Insertion for DSA-MP Hybrid Lithography. ISPD 2016: 39-46 - [c140]Xiaoqing Xu, Tetsuaki Matsunawa, Shigeki Nojima, Chikaaki Kodama, Toshiya Kotani, David Z. Pan:
A Machine Learning Based Framework for Sub-Resolution Assist Feature Generation. ISPD 2016: 161-168 - [r4]Minsik Cho, David Z. Pan:
Global Routing. Encyclopedia of Algorithms 2016: 856-858 - [r3]Bei Yu, David Z. Pan:
Layout Decomposition for Triple Patterning. Encyclopedia of Algorithms 2016: 1062-1065 - 2015
- [j46]Bei Yu, Kun Yuan, Duo Ding, David Z. Pan:
Layout Decomposition for Triple Patterning Lithography. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34(3): 433-446 (2015) - [j45]Subhendu Roy, Pavlos M. Mattheakis, Laurent Masse-Navette, David Z. Pan:
Clock Tree Resynthesis for Multi-Corner Multi-Mode Timing Closure. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34(4): 589-602 (2015) - [j44]Xiaoqing Xu, Brian Cline, Greg Yeric, Bei Yu, David Z. Pan:
Self-Aligned Double Patterning Aware Pin Access and Standard Cell Layout Co-Optimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34(5): 699-712 (2015) - [j43]Bei Yu, Xiaoqing Xu, Jhih-Rong Gao, Yibo Lin, Zhuo Li, Charles J. Alpert, David Z. Pan:
Methodology for Standard Cell Compliance and Detailed Placement for Triple Patterning Lithography. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34(5): 726-739 (2015) - [j42]Ye Zhang, Wai-Shing Luk, Yunfeng Yang, Hai Zhou, Changhao Yan, David Z. Pan, Xuan Zeng:
Layout Decomposition with Pairwise Coloring and Adaptive Multi-Start for Triple Patterning Lithography. ACM Trans. Design Autom. Electr. Syst. 21(1): 2:1-2:25 (2015) - [c139]Subhendu Roy, Mihir R. Choudhury, Ruchir Puri, David Z. Pan:
Polynomial time algorithm for area and power efficient adder synthesis in high-performance designs. ASP-DAC 2015: 249-254 - [c138]Bei Yu, David Z. Pan, Tetsuaki Matsunawa, Xuan Zeng:
Machine learning and pattern matching in physical design. ASP-DAC 2015: 286-293 - [c137]Jiwoo Pak, Bei Yu, David Z. Pan:
Electromigration-aware redundant via insertion. ASP-DAC 2015: 544-549 - [c136]Xiaoqing Xu, Bei Yu, Jhih-Rong Gao, Che-Lun Hsu, David Z. Pan:
PARR: pin access planning and regular routing for self-aligned double patterning. DAC 2015: 28:1-28:6 - [c135]Yibo Lin, Bei Yu, David Z. Pan:
High performance dummy fill insertion with coupling and uniformity constraints. DAC 2015: 71:1-71:6 - [c134]Subhendu Roy, Derong Liu, Junhyung Um, David Z. Pan:
OSFA: a new paradigm of gate-sizing for power/performance optimizations under multiple operating conditions. DAC 2015: 129:1-129:6 - [c133]Keith A. Campbell, Pranay Vissa, David Z. Pan, Deming Chen:
High-level synthesis of error detecting cores through low-cost modulo-3 shadow datapaths. DAC 2015: 161:1-161:6 - [c132]David Z. Pan, Lars Liebmann, Bei Yu, Xiaoqing Xu, Yibo Lin:
Pushing multiple patterning in sub-10nm: are we ready? DAC 2015: 197:1-197:6 - [c131]Jiaojiao Ou, Bei Yu, Jhih-Rong Gao, David Z. Pan, Moshe Preil, Azat Latypov:
Directed Self-Assembly Based Cut Mask Optimization for Unidirectional Design. ACM Great Lakes Symposium on VLSI 2015: 83-86 - [c130]Subhendu Roy, David Z. Pan, Pavlos M. Mattheakis, Peter S. Colyer, Laurent Masse-Navette, Pierre-Olivier Ribet:
Skew Bounded Buffer Tree Resynthesis For Clock Power Optimization. ACM Great Lakes Symposium on VLSI 2015: 87-90 - [c129]Wei Ye, Bei Yu, David Z. Pan, Yongchan Ban, Lars Liebmann:
Standard Cell Layout Regularity and Pin Access Optimization Considering Middle-of-Line. ACM Great Lakes Symposium on VLSI 2015: 289-294 - [c128]Bei Yu, Derong Liu, Salim Chowdhury, David Z. Pan:
TILA: Timing-Driven Incremental Layer Assignment. ICCAD 2015: 110-117 - [c127]Andrew B. Kahng, Mulong Luo, Gi-Joon Nam, Siddhartha Nath, David Z. Pan, Gabriel Robins:
Toward Metrics of Design Automation Research Impact. ICCAD 2015: 263-270 - [c126]Yibo Lin, Bei Yu, Biying Xu, David Z. Pan:
Triple Patterning Aware Detailed Placement Toward Zero Cross-Row Middle-of-Line Conflict. ICCAD 2015: 396-403 - [c125]Chen-Hsuan Lin, Subhendu Roy, Chun-Yao Wang, David Z. Pan, Deming Chen:
CSL: Coordinated and scalable logic synthesis techniques for effective NBTI reduction. ICCD 2015: 236-243 - [i14]Bei Yu, Kun Yuan, Jhih-Rong Gao, David Z. Pan:
E-BLOW: E-Beam Lithography Overlapping aware Stencil Planning for MCC System. CoRR abs/1502.00621 (2015) - 2014
- [j41]Moongon Jung, Joydeep Mitra, David Z. Pan, Sung Kyu Lim:
TSV stress-aware full-chip mechanical reliability analysis and optimization for 3D IC. Commun. ACM 57(1): 107-115 (2014) - [j40]Subhendu Roy, Mihir R. Choudhury, Ruchir Puri, David Z. Pan:
Towards Optimal Performance-Area Trade-Off in Adders by Synthesis of Parallel Prefix Structures. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(10): 1517-1530 (2014) - [j39]Jiwoo Pak, Sung Kyu Lim, David Z. Pan:
Electromigration Study for Multiscale Power/Ground Vias in TSV-Based 3-D ICs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(12): 1873-1885 (2014) - [j38]Naehyuck Chang, David Z. Pan, Yuan Xie:
Editorial: ACM Transactions on Design Automation of Electronics Systems and Beyond. ACM Trans. Design Autom. Electr. Syst. 20(1): 1:1-1:2 (2014) - [c124]Jhih-Rong Gao, Bei Yu, David Z. Pan:
Self-aligned double patterning layout decomposition with complementary e-beam lithography. ASP-DAC 2014: 143-148 - [c123]Yilin Zhang, Salim Chowdhury, David Z. Pan:
BOB-router: A new buffering-aware global router with over-the-block routing resources optimization. ASP-DAC 2014: 513-518 - [c122]Jhih-Rong Gao, Xiaoqing Xu, Bei Yu, David Z. Pan:
MOSAIC: Mask Optimizing Solution With Process Window Aware Inverse Correction. DAC 2014: 52:1-52:6 - [c121]Bei Yu, David Z. Pan:
Layout Decomposition for Quadruple Patterning Lithography and Beyond. DAC 2014: 53:1-53:6 - [c120]Yilin Zhang, David Z. Pan:
Timing-driven, over-the-block rectilinear steiner tree construction with pre-buffering and slew constraints. ISPD 2014: 29-36 - [c119]Subhendu Roy, Pavlos M. Mattheakis, Laurent Masse-Navette, David Z. Pan:
Clock tree resynthesis for multi-corner multi-mode timing closure. ISPD 2014: 69-76 - [c118]Xiaoqing Xu, Brian Cline, Greg Yeric, Bei Yu, David Z. Pan:
Self-aligned double patterning aware pin access and standard cell layout co-optimization. ISPD 2014: 101-108 - [c117]Subhendu Roy, David Z. Pan:
Reliability Aware Gate Sizing Combating NBTI and Oxide Breakdown. VLSID 2014: 38-43 - [i13]Bei Yu, Jhih-Rong Gao, David Z. Pan:
L-Shape based Layout Fracturing for E-Beam Lithography. CoRR abs/1402.2420 (2014) - [i12]Bei Yu, Jhih-Rong Gao, David Z. Pan:
Triple Patterning Lithography (TPL) Layout Decomposition using End-Cutting. CoRR abs/1402.2425 (2014) - [i11]Bei Yu, Kun Yuan, Jhih-Rong Gao, David Z. Pan:
E-BLOW: E-Beam Lithography Overlapping aware Stencil Planning for MCC System. CoRR abs/1402.2435 (2014) - [i10]Jhih-Rong Gao, Bei Yu, Ru Huang, David Z. Pan:
Self-Aligned Double Patterning Friendly Configuration for Standard Cell Library Considering Placement. CoRR abs/1402.2442 (2014) - [i9]Bei Yu, Kun Yuan, Boyang Zhang, Duo Ding, David Z. Pan:
Layout decomposition for triple patterning lithography. CoRR abs/1402.2459 (2014) - [i8]Bei Yu, Xiaoqing Xu, Jhih-Rong Gao, David Z. Pan:
Methodology for standard cell compliance and detailed placement for triple patterning lithography. CoRR abs/1402.2635 (2014) - [i7]Bei Yu, Yen-Hung Lin, Gerard Luk-Pat, Duo Ding, Kevin Lucas, David Z. Pan:
A High-Performance Triple Patterning Layout Decomposer with Balanced Density. CoRR abs/1402.2890 (2014) - [i6]Duo Ding, Bei Yu, David Z. Pan:
GLOW: A global router for low-power thermal-reliable interconnect synthesis using photonic wavelength multiplexing. CoRR abs/1402.2899 (2014) - [i5]Duo Ding, Bei Yu, Joydeep Ghosh, David Z. Pan:
EPIC: Efficient prediction of IC manufacturing hotspots with a unified meta-classification formulation. CoRR abs/1402.2904 (2014) - [i4]Yen-Hung Lin, Bei Yu, David Z. Pan, Yih-Lang Li:
TRIAD: a triple patterning lithography aware detailed router. CoRR abs/1402.2906 (2014) - [i3]Jhih-Rong Gao, Bei Yu, David Z. Pan:
Lithography Hotspot Detection and Mitigation in Nanometer VLSI. CoRR abs/1402.3150 (2014) - [i2]Bei Yu, David Z. Pan:
Layout Decomposition for Quadruple Patterning Lithography and Beyond. CoRR abs/1404.0321 (2014) - [i1]Bei Yu, Subhendu Roy, Jhih-Rong Gao, David Z. Pan:
Triple Patterning Lithography (TPL) Layout Decomposition using End-Cutting (JM3 Special Session). CoRR abs/1408.0407 (2014) - 2013
- [j37]Samuel I. Ward, Myung-Chul Kim, Natarajan Viswanathan, Zhuo Li, Charles J. Alpert, Earl E. Swartzlander Jr., David Z. Pan:
Structure-Aware Placement Techniques for Designs With Datapaths. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32(2): 228-241 (2013) - [j36]Krit Athikulwongse, Jae-Seok Yang, David Z. Pan, Sung Kyu Lim:
Impact of Mechanical Stress on the Full Chip Timing for Through-Silicon-Via-based 3-D ICs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32(6): 905-917 (2013) - [j35]Ashutosh Chakraborty, David Z. Pan:
Skew Management of NBTI Impacted Gated Clock Trees. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32(6): 918-927 (2013) - [j34]Wooyoung Jang, David Z. Pan:
Chemical-Mechanical Polishing-Aware Application-Specific 3D NoC Design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32(6): 940-951 (2013) - [j33]David Z. Pan, Bei Yu, Jhih-Rong Gao:
Design for Manufacturing With Emerging Nanolithography. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32(10): 1453-1472 (2013) - [j32]Moongon Jung, David Z. Pan, Sung Kyu Lim:
Chip/Package Mechanical Stress Impact on 3-D IC Reliability and Mobility Variations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32(11): 1694-1707 (2013) - [c116]Jhih-Rong Gao, Bei Yu, Duo Ding, David Z. Pan:
Lithography hotspot detection and mitigation in nanometer VLSI. ASICON 2013: 1-4 - [c115]Bei Yu, Jhih-Rong Gao, David Z. Pan:
L-shape based layout fracturing for e-beam lithography. ASP-DAC 2013: 249-254 - [c114]Subhendu Roy, Mihir R. Choudhury, Ruchir Puri, David Z. Pan:
Towards optimal performance-area trade-off in adders by synthesis of parallel prefix structures. DAC 2013: 48:1-48:8 - [c113]Bei Yu, Kun Yuan, Jhih-Rong Gao, David Z. Pan:
E-BLOW: e-beam lithography overlapping aware stencil planning for MCC system. DAC 2013: 70:1-70:7 - [c112]Yang Li, David Z. Pan:
An accurate semi-analytical framework for full-chip TSV-induced stress modeling. DAC 2013: 181:1-181:8 - [c111]Bei Yu, Yen-Hung Lin, Gerard Luk-Pat, Duo Ding, Kevin Lucas, David Z. Pan:
A high-performance triple patterning layout decomposer with balanced density. ICCAD 2013: 163-169 - [c110]Bei Yu, Xiaoqing Xu, Jhih-Rong Gao, David Z. Pan:
Methodology for standard cell compliance and detailed placement for triple patterning lithography. ICCAD 2013: 349-356 - [c109]Jiwoo Pak, Sung Kyu Lim, David Z. Pan:
Electromigration study for multi-scale power/ground vias in TSV-based 3D ICs. ICCAD 2013: 379-386 - [c108]Samuel I. Ward, Natarajan Viswanathan, Nancy Y. Zhou, Cliff C. N. Sze, Zhuo Li, Charles J. Alpert, David Z. Pan:
Clock power minimization using structured latch templates and decision tree induction. ICCAD 2013: 599-606 - 2012
- [j31]Anand Ramalingam, Ashish Kumar Singh, Sani R. Nassif, Gi-Joon Nam, Michael Orshansky, David Z. Pan:
An accurate sparse-matrix based framework for statistical static timing analysis. Integr. 45(4): 365-375 (2012) - [j30]Kun Yuan, Bei Yu, David Z. Pan:
E-Beam Lithography Stencil Planning and Optimization With Overlapped Characters. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31(2): 167-179 (2012) - [j29]Moongon Jung, Joydeep Mitra, David Z. Pan, Sung Kyu Lim:
TSV Stress-Aware Full-Chip Mechanical Reliability Analysis and Optimization for 3-D IC. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31(8): 1194-1207 (2012) - [j28]Wooyoung Jang, David Z. Pan:
A3MAP: Architecture-aware analytic mapping for networks-on-chip. ACM Trans. Design Autom. Electr. Syst. 17(3): 26:1-26:22 (2012) - [j27]Ou He, Sheqin Dong, Wooyoung Jang, Jinian Bian, David Z. Pan:
UNISM: Unified Scheduling and Mapping for General Networks on Chip. IEEE Trans. Very Large Scale Integr. Syst. 20(8): 1496-1509 (2012) - [c107]Vijay Janapa Reddi, David Z. Pan, Sani R. Nassif, Keith A. Bowman:
Robust and resilient designs from the bottom-up: Technology, CAD, circuit, and system issues. ASP-DAC 2012: 7-16 - [c106]Duo Ding, Bei Yu, Joydeep Ghosh, David Z. Pan:
EPIC: Efficient prediction of IC manufacturing hotspots with a unified meta-classification formulation. ASP-DAC 2012: 263-270 - [c105]Duo Ding, Bei Yu, David Z. Pan:
GLOW: A global router for low-power thermal-reliable interconnect synthesis using photonic wavelength multiplexing. ASP-DAC 2012: 621-626 - [c104]David Z. Pan, Sung Kyu Lim, Krit Athikulwongse, Moongon Jung, Joydeep Mitra, Jiwoo Pak, Mohit Pathak, Jae-Seok Yang:
Design for manufacturability and reliability for TSV-based 3D ICs. ASP-DAC 2012: 750-755 - [c103]Moongon Jung, David Z. Pan, Sung Kyu Lim:
Chip/package co-analysis of thermo-mechanical stress and reliability in TSV-based 3D ICs. DAC 2012: 317-326 - [c102]Samuel I. Ward, Duo Ding, David Z. Pan:
PADE: a high-performance placer with automatic datapath extraction and evaluation through high dimensional data learning. DAC 2012: 756-761 - [c101]Yen-Hung Lin, Bei Yu, David Z. Pan, Yih-Lang Li:
TRIAD: A triple patterning lithography aware detailed router. ICCAD 2012: 123-129 - [c100]Yilin Zhang, Ashutosh Chakraborty, Salim Chowdhury, David Z. Pan:
Reclaiming over-the-IP-block routing resources with buffering-aware rectilinear Steiner minimum tree construction. ICCAD 2012: 137-143 - [c99]Bei Yu, Jhih-Rong Gao, Duo Ding, Yongchan Ban, Jae-Seok Yang, Kun Yuan, Minsik Cho, David Z. Pan:
Dealing with IC manufacturability in extreme scaling (Embedded tutorial paper). ICCAD 2012: 240-242 - [c98]Jiwoo Pak, Sung Kyu Lim, David Z. Pan:
Electromigration-aware routing for 3D ICs with stress-aware EM modeling. ICCAD 2012: 325-332 - [c97]Jhih-Rong Gao, David Z. Pan:
Flexible self-aligned double patterning aware detailed routing with prescribed layout planning. ISPD 2012: 25-32 - [c96]Samuel I. Ward, Myung-Chul Kim, Natarajan Viswanathan, Zhuo Li, Charles J. Alpert, Earl E. Swartzlander Jr., David Z. Pan:
Keep it straight: teaching placement how to better handle designs with datapaths. ISPD 2012: 79-86 - [c95]David Z. Pan, Jhih-Rong Gao, Bei Yu:
VLSI CAD for emerging nanolithography. VLSI-DAT 2012: 1-4 - 2011
- [j26]Yongchan Ban, David Z. Pan:
Modeling of Layout Aware Line-Edge Roughness and Poly Optimization for Leakage Minimization. IEEE J. Emerg. Sel. Topics Circuits Syst. 1(2): 150-159 (2011) - [j25]Wooyoung Jang, David Z. Pan:
A Voltage-Frequency Island Aware Energy Optimization Framework for Networks-on-Chip. IEEE J. Emerg. Sel. Topics Circuits Syst. 1(3): 420-432 (2011) - [j24]Anand Rajaram, David Z. Pan:
Robust Chip-Level Clock Tree Synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30(6): 877-890 (2011) - [j23]Wooyoung Jang, David Z. Pan:
Application-Aware NoC Design for Efficient SDRAM Access. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30(10): 1521-1533 (2011) - [j22]Duo Ding, J. Andres Torres, David Z. Pan:
High Performance Lithography Hotspot Detection With Successively Refined Pattern Identifications and Machine Learning. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30(11): 1621-1634 (2011) - [c94]Shashikanth Bobba, Ashutosh Chakraborty, Olivier Thomas, Perrine Batude, Thomas Ernst, Olivier Faynot, David Z. Pan, Giovanni De Micheli:
CELONCEL: Effective design technique for 3-D monolithic integration targeting high performance integrated circuits. ASP-DAC 2011: 336-343 - [c93]Chul-Hong Park, David Z. Pan, Kevin Lucas:
Exploration of VLSI CAD researches for early design rule evaluation. ASP-DAC 2011: 405-406 - [c92]Ashutosh Chakraborty, David Z. Pan:
Controlling NBTI degradation during static burn-in testing. ASP-DAC 2011: 597-602 - [c91]Jae-Seok Yang, Jiwoo Pak, Xin Zhao, Sung Kyu Lim, David Z. Pan:
Robust Clock Tree Synthesis with timing yield optimization for 3D-ICs. ASP-DAC 2011: 621-626 - [c90]Duo Ding, Andres J. Torres, Fedor G. Pikus, David Z. Pan:
High performance lithographic hotspot detection using hierarchically refined machine learning. ASP-DAC 2011: 775-780 - [c89]Moongon Jung, Joydeep Mitra, David Z. Pan, Sung Kyu Lim:
TSV stress-aware full-chip mechanical reliability analysis and optimization for 3D IC. DAC 2011: 188-193 - [c88]Yongchan Ban, Kevin Lucas, David Z. Pan:
Flexible 2D layout decomposition framework for spacer-type double pattering lithography. DAC 2011: 789-794 - [c87]Duo Ding, Jhih-Rong Gao, Kun Yuan, David Z. Pan:
AENEID: a generic lithography-friendly detailed router based on post-RET data learning and hotspot detection. DAC 2011: 795-800 - [c86]Bei Yu, Kun Yuan, Boyang Zhang, Duo Ding, David Z. Pan:
Layout decomposition for triple patterning lithography. ICCAD 2011: 1-8 - [c85]Wooyoung Jang, Ou He, Jae-Seok Yang, David Z. Pan:
Chemical-mechanical polishing aware application-specific 3D NoC design. ICCAD 2011: 207-212 - [c84]Yen-Hung Lin, Yongchan Ban, David Z. Pan, Yih-Lang Li:
Doppler: DPL-aware and OPC-friendly gridless detailed routing with mask density balancing. ICCAD 2011: 283-289 - [c83]Mohit Pathak, Jiwoo Pak, David Z. Pan, Sung Kyu Lim:
Electromigration modeling and full-chip reliability analysis for BEOL interconnect in TSV-based 3D ICs. ICCAD 2011: 555-562 - [c82]Moongon Jung, Xi Liu, Suresh K. Sitaraman, David Z. Pan, Sung Kyu Lim:
Full-chip through-silicon-via interfacial crack analysis and optimization for 3D IC. ICCAD 2011: 563-570 - [c81]Kun Yuan, David Z. Pan:
E-beam lithography stencil planning and optimization with overlapped characters. ISPD 2011: 151-158 - 2010
- [j21]David Z. Pan, Minsik Cho, Kun Yuan:
Manufacturability Aware Routing in Nanometer VLSI. Found. Trends Electron. Des. Autom. 4(1): 1-97 (2010) - [j20]Kun Yuan, Jae-Seok Yang, David Z. Pan:
Double Patterning Layout Decomposition for Simultaneous Conflict and Stitch Minimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(2): 185-196 (2010) - [j19]Ashutosh Chakraborty, Sean X. Shi, David Z. Pan:
Stress Aware Layout Optimization Leveraging Active Area Dependent Mobility Enhancement. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(10): 1533-1545 (2010) - [j18]Wooyoung Jang, David Z. Pan:
An SDRAM-Aware Router for Networks-on-Chip. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(10): 1572-1585 (2010) - [j17]Anand Rajaram, David Z. Pan:
MeshWorks: A Comprehensive Framework for Optimized Clock Mesh Network Synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(12): 1945-1958 (2010) - [c80]Wooyoung Jang, David Z. Pan:
A3MAP: architecture-aware analytic mapping for networks-on-chip. ASP-DAC 2010: 523-528 - [c79]Jae-Seok Yang, Katrina Lu, Minsik Cho, Kun Yuan, David Z. Pan:
A new graph-theoretic, multi-objective layout decomposition framework for double patterning lithography. ASP-DAC 2010: 637-644 - [c78]Yongchan Ban, David Z. Pan:
Compact modeling and robust layout optimization for contacts in deep sub-wavelength lithography. DAC 2010: 408-411 - [c77]Wooyoung Jang, David Z. Pan:
Application-aware NoC design for efficient SDRAM access. DAC 2010: 453-456 - [c76]Jae-Seok Yang, Krit Athikulwongse, Young-Joon Lee, Sung Kyu Lim, David Z. Pan:
TSV stress aware timing analysis with applications to 3D-IC layout optimization. DAC 2010: 803-806 - [c75]Kun Yuan, David Z. Pan:
WISDOM: Wire spreading enhanced decomposition of masks in Double Patterning Lithography. ICCAD 2010: 32-38 - [c74]Minsik Cho, David Z. Pan, Ruchir Puri:
Novel binary linear programming for high performance clock mesh synthesis. ICCAD 2010: 438-443 - [c73]Krit Athikulwongse, Ashutosh Chakraborty, Jae-Seok Yang, David Z. Pan, Sung Kyu Lim:
Stress-driven 3D-IC placement with TSV keep-out zone and regularity study. ICCAD 2010: 669-674 - [c72]Ashutosh Chakraborty, David Z. Pan:
PASAP: power aware structured ASIC placement. ISLPED 2010: 395-400 - [c71]Yongchan Ban, Savithri Sundareswaran, David Z. Pan:
Total sensitivity based dfm optimization of standard library cells. ISPD 2010: 113-120 - [c70]Ashutosh Chakraborty, David Z. Pan:
Skew management of NBTI impacted gated clock trees. ISPD 2010: 127-133
2000 – 2009
- 2009
- [j16]Minsik Cho, Kun Yuan, Yongchan Ban, David Z. Pan:
ELIAD: Efficient Lithography Aware Detailed Routing Algorithm With Compact and Macro Post-OPC Printability Prediction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(7): 1006-1016 (2009) - [j15]Minsik Cho, Katrina Lu, Kun Yuan, David Z. Pan:
BoxRouter 2.0: A hybrid and robust global router with layer assignment for routability. ACM Trans. Design Autom. Electr. Syst. 14(2): 32:1-32:21 (2009) - [c69]Kun Yuan, Katrina Lu, David Z. Pan:
Double patterning lithography friendly detailed routing with redundant via consideration. DAC 2009: 63-66 - [c68]Duo Ding, Yilin Zhang, Haiyu Huang, Ray T. Chen, David Z. Pan:
O-Router: an optical routing framework for low power on-chip silicon nano-photonic integration. DAC 2009: 264-269 - [c67]Ashutosh Chakraborty, Anurag Kumar, David Z. Pan:
RegPlace: a high quality open-source placement framework for structured ASICs. DAC 2009: 442-447 - [c66]Wooyoung Jang, David Z. Pan:
An SDRAM-aware router for Networks-on-Chip. DAC 2009: 800-805 - [c65]Ashutosh Chakraborty, Gokul Ganesan, Anand Rajaram, David Z. Pan:
Analysis and optimization of NBTI induced clock skew in gated clock trees. DATE 2009: 296-299 - [c64]Ashutosh Chakraborty, David Z. Pan:
On stress aware active area sizing, gate sizing, and repeater insertion. ISPD 2009: 35-42 - [c63]Kun Yuan, Jae-Seok Yang, David Z. Pan:
Double patterning layout decomposition for simultaneous conflict and stitch minimization. ISPD 2009: 107-114 - [c62]Duo Ding, David Z. Pan:
OIL: a nano-photonics optical interconnect library for a new photonic networks-on-chip architecture. SLIP 2009: 11-18 - 2008
- [j14]Patrick H. Madden, David Z. Pan:
Guest Editorial. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(4): 608-609 (2008) - [j13]Minsik Cho, Hua Xiang, Ruchir Puri, David Z. Pan:
Track Routing and Optimization for Yield. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(5): 872-882 (2008) - [j12]Minsik Cho, David Z. Pan:
A High-Performance Droplet Routing Algorithm for Digital Microfluidic Biochips. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(10): 1714-1724 (2008) - [j11]David Z. Pan, Gi-Joon Nam:
Guest Editorial. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(12): 2105-2106 (2008) - [j10]Tung-Chieh Chen, Minsik Cho, David Z. Pan, Yao-Wen Chang:
Metal-Density-Driven Placement for CMP Variation and Routability. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(12): 2145-2155 (2008) - [j9]Minsik Cho, David Z. Pan:
Fast Substrate Noise Aware Floorplanning for Mixed Signal SOC Designs. IEEE Trans. Very Large Scale Integr. Syst. 16(12): 1713-1717 (2008) - [c61]David Z. Pan, Minsik Cho:
Synergistic physical synthesis for manufacturability and variability in 45nm designs and beyond. ASP-DAC 2008: 220-225 - [c60]Anand Rajaram, David Z. Pan:
MeshWorks: An efficient framework for planning, synthesis and optimization of clock mesh networks. ASP-DAC 2008: 250-257 - [c59]Tao Luo, David Z. Pan:
DPlace2.0: A stable and efficient analytical placement based on diffusion. ASP-DAC 2008: 346-351 - [c58]Tao Luo, David Newmark, David Z. Pan:
Total power optimization combining placement, sizing and multi-Vt through slack distribution management. ASP-DAC 2008: 352-357 - [c57]Peng Yu, Xi Chen, David Z. Pan, Andrew D. Ellington:
Synthetic Biology Design and Analysis: A Case Study of Frequency Entrained Biological Clock. BIBM 2008: 329-334 - [c56]Minsik Cho, Kun Yuan, Yongchan Ban, David Z. Pan:
ELIAD: efficient lithography aware detailed router with compact post-OPC printability prediction. DAC 2008: 504-509 - [c55]Tung-Chieh Chen, Ashutosh Chakraborty, David Z. Pan:
An integrated nonlinear placement framework with congestion and porosity aware buffer planning. DAC 2008: 702-707 - [c54]Anand Rajaram, David Z. Pan:
Robust chip-level clock tree synthesis for SOC designs. DAC 2008: 720-723 - [c53]Ashutosh Chakraborty, Sean X. Shi, David Z. Pan:
Layout Level Timing Optimization by Leveraging Active Area Dependent Mobility of Strained-Silicon Devices. DATE 2008: 849-855 - [c52]Sean X. Shi, Anand Ramalingam, Daifeng Wang, David Z. Pan:
Latch Modeling for Statistical Timing Analysis. DATE 2008: 1136-1141 - [c51]David Z. Pan, Stephen Renwick, Vivek Singh, Judy Huckabay:
Nanolithography and CAD challenges for 32nm/22nm and beyond. ICCAD 2008: 6 - [c50]Tao Luo, David A. Papa, Zhuo Li, Chin Ngai Sze, Charles J. Alpert, David Z. Pan:
Pyramids: an efficient computational geometry-based approach for timing-driven placement. ICCAD 2008: 204-211 - [c49]Wooyoung Jang, Duo Ding, David Z. Pan:
A voltage-frequency island aware energy optimization framework for networks-on-chip. ICCAD 2008: 264-269 - [c48]Jae-Seok Yang, David Z. Pan:
Overlay aware interconnect and timing variation modeling for double patterning technology. ICCAD 2008: 488-493 - [c47]Minsik Cho, Yongchan Ban, David Z. Pan:
Double patterning technology friendly detailed routing. ICCAD 2008: 506-511 - [c46]Tung-Chieh Chen, Minsik Cho, David Z. Pan, Yao-Wen Chang:
Metal-density driven placement for cmp variation and routability. ISPD 2008: 31-38 - [c45]Minsik Cho, David Z. Pan:
A high-performance droplet router for digital microfluidic biochips. ISPD 2008: 200-206 - [c44]David Z. Pan:
Synergistic modeling and optimization for nanometer IC design/manufacturing integration. SBCCI 2008: 2 - [c43]David Z. Pan:
Lithography friendly routing: from construct-by-correction to correct-by-construction. SBCCI 2008: 6 - [e2]David Z. Pan, Gi-Joon Nam:
Proceedings of the 2008 International Symposium on Physical Design, ISPD 2008, Portland, Oregon, USA, April 13-16, 2008. ACM 2008, ISBN 978-1-60558-048-7 [contents] - [r2]Minsik Cho, Joydeep Mitra, David Z. Pan:
Manufacturability-Aware Routing. Handbook of Algorithms for Physical Design Automation 2008 - [r1]David Z. Pan, Bill Halpin, Haoxing Ren:
Timing-Driven Placement. Handbook of Algorithms for Physical Design Automation 2008 - 2007
- [j8]Anand Ramalingam, Anirudh Devgan, David Z. Pan:
Wakeup Scheduling in MTCMOS Circuits Using Successive Relaxation to Minimize Ground Bounce. J. Low Power Electron. 3(1): 28-35 (2007) - [j7]Minsik Cho, David Z. Pan:
BoxRouter: A New Global Router Based on Box Expansion and Progressive ILP. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(12): 2130-2143 (2007) - [j6]Haoxing Ren, David Z. Pan, Charles J. Alpert, Paul G. Villarrubia, Gi-Joon Nam:
Diffusion-Based Placement Migration With Application on Legalization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(12): 2158-2172 (2007) - [c42]Haoxing Ren, David Z. Pan, Charles J. Alpert, Gi-Joon Nam, Paul G. Villarrubia:
Hippocrates: First-Do-No-Harm Detailed Placement. ASP-DAC 2007: 141-146 - [c41]Minsik Cho, Hua Xiang, Ruchir Puri, David Z. Pan:
TROY: Track Router with Yield-driven Wire Planning. DAC 2007: 55-58 - [c40]Anand Ramalingam, Ashish Kumar Singh, Sani R. Nassif, Michael Orshansky, David Z. Pan:
Accurate Waveform Modeling using Singular Value Decomposition with Applications to Timing Analysis. DAC 2007: 148-153 - [c39]Minsik Cho, Katrina Lu, Kun Yuan, David Z. Pan:
BoxRouter 2.0: architecture and implementation of a hybrid and robust global router. ICCAD 2007: 503-508 - [c38]Peng Yu, David Z. Pan:
TIP-OPC: a new topological invariant paradigm for pixel based optical proximity correction. ICCAD 2007: 847-853 - [c37]Peng Yu, David Z. Pan:
A novel intensity based optical proximity correction algorithm with speedup in lithography simulation. ICCAD 2007: 854-859 - [c36]Anand Ramalingam, Giri Devarayanadurg, David Z. Pan:
Accurate power grid analysis with behavioral transistor network modeling. ISPD 2007: 43-50 - [c35]Gi-Joon Nam, Mehmet Can Yildiz, David Z. Pan, Patrick H. Madden:
ISPD placement contest updates and ISPD 2007 global routing contest. ISPD 2007: 167 - [c34]Joon-Sung Yang, Anand Rajaram, Ninghy Shi, Jian Chen, David Z. Pan:
Sensitivity Based Link Insertion for Variation Tolerant Clock Network Synthesis. ISQED 2007: 398-403 - [p1]Tao Luo, David Z. Pan:
DPlace: Anchor Cell-Based Quadratic Placement with Linear Objective. Modern Circuit Placement 2007: 39-58 - [e1]Patrick H. Madden, David Z. Pan:
Proceedings of the 2007 International Symposium on Physical Design, ISPD 2007, Austin, Texas, USA, March 18-21, 2007. ACM 2007, ISBN 978-1-59593-613-4 [contents] - 2006
- [c33]Anand Ramalingam, Sreekumar V. Kodakara, Anirudh Devgan, David Z. Pan:
Robust analytical gate delay modeling for low voltage circuits. ASP-DAC 2006: 61-66 - [c32]Sean X. Shi, David Z. Pan:
Wire sizing with scattering effect for nanoscale interconnection. ASP-DAC 2006: 503-508 - [c31]Minsik Cho, Hongjoong Shin, David Z. Pan:
Fast substrate noise-aware floorplanning with preference directed graph for mixed-signal SOCs. ASP-DAC 2006: 765-770 - [c30]Minsik Cho, David Z. Pan:
BoxRouter: a new global router based on box expansion and progressive ILP. DAC 2006: 373-378 - [c29]Peng Yu, Sean X. Shi, David Z. Pan:
Process variation aware OPC with variational lithography modeling. DAC 2006: 785-790 - [c28]Tao Luo, David Newmark, David Z. Pan:
A new LP based incremental timing driven placement for high performance designs. DAC 2006: 1115-1120 - [c27]Anand Ramalingam, Gi-Joon Nam, Ashish Kumar Singh, Michael Orshansky, Sani R. Nassif, David Z. Pan:
An accurate sparse matrix based framework for statistical static timing analysis. ICCAD 2006: 231-236 - [c26]Sean X. Shi, Peng Yu, David Z. Pan:
A unified non-rectangular device and circuit simulation model for timing and power. ICCAD 2006: 423-428 - [c25]Minsik Cho, David Z. Pan, Hua Xiang, Ruchir Puri:
Wire density driven global routing for CMP variation and timing. ICCAD 2006: 487-492 - [c24]Avijit Dutta, David Z. Pan:
Partial Functional Manipulation Based Wirelength Minimization. ICCD 2006: 344-349 - [c23]Anand Rajaram, David Z. Pan:
Variation tolerant buffered clock network synthesis with cross links. ISPD 2006: 157-164 - [c22]Anand Rajaram, David Z. Pan:
Fast Incremental Link Insertion in Clock Networks for Skew Variability Reduction. ISQED 2006: 79-84 - [c21]Andrew Havlir, David Z. Pan:
Simultaneous Statistical Delay and Slew Optimization for Interconnect Pipelines. ISQED 2006: 171-178 - [c20]Anand Ramalingam, David Z. Pan, Frank Liu, Sani R. Nassif:
Accurate Thermal Analysis Considering Nonlinear Thermal Conductivity. ISQED 2006: 644-649 - [c19]Minsik Cho, David Z. Pan:
PEAKASO: Peak-Temperature Aware Scan-Vector Optimization. VTS 2006: 52-57 - 2005
- [j5]Haoxing Ren, David Zhigang Pan, David S. Kung:
Sensitivity guided net weighting for placement-driven synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(5): 711-721 (2005) - [c18]Anand Ramalingam, Bin Zhang, Anirudh Devgan, David Z. Pan:
Sleep transistor sizing using timing criticality and temporal currents. ASP-DAC 2005: 1094-1097 - [c17]Gang Xu, Ruiqi Tian, David Z. Pan, Martin D. F. Wong:
CMP aware shuttle mask floorplanning. ASP-DAC 2005: 1111-1114 - [c16]Gang Xu, Li-Da Huang, David Z. Pan, Martin D. F. Wong:
Redundant-via enhanced maze routing for yield improvement. ASP-DAC 2005: 1148-1151 - [c15]Joydeep Mitra, Peng Yu, David Zhigang Pan:
RADAR: RET-aware detailed routing using fast lithography simulations. DAC 2005: 369-372 - [c14]Haoxing Ren, David Zhigang Pan, Charles J. Alpert, Paul Villarrubia:
Diffusion-based placement migration. DAC 2005: 515-520 - [c13]Tao Luo, Haoxing Ren, Charles J. Alpert, David Zhigang Pan:
Computational geometry based placement migration. ICCAD 2005: 41-47 - [c12]Minsik Cho, Suhail Ahmed, David Z. Pan:
TACO: temperature aware clock-tree optimization. ICCAD 2005: 582-587 - [c11]Anand Rajaram, David Z. Pan, Jiang Hu:
Improved algorithms for link-based non-tree clock networks for skew variability reduction. ISPD 2005: 55-62 - 2004
- [c10]Haoxing Ren, David Zhigang Pan, Paul Villarrubia:
True crosstalk aware incremental placement with noise map. ICCAD 2004: 402-409 - [c9]Haoxing Ren, David Zhigang Pan, David S. Kung:
Sensitivity guided net weighting for placement driven synthesis. ISPD 2004: 10-17 - 2003
- [j4]Chin-Chih Chang, Jason Cong, David Zhigang Pan, Xin Yuan:
Multilevel global placement with congestion control. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(4): 395-409 (2003) - [c8]Ruchir Puri, Leon Stok, John M. Cohn, David S. Kung, David Z. Pan, Dennis Sylvester, Ashish Srivastava, Sarvesh H. Kulkarni:
Pushing ASIC performance in a power envelope. DAC 2003: 788-793 - 2002
- [j3]Jason Cong, David Zhigang Pan:
Wire width planning for interconnect performance optimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(3): 319-329 (2002) - [c7]Chin-Chih Chang, Jason Cong, David Zhigang Pan:
Physical hierarchy generation with routing congestion control. ISPD 2002: 36-41 - 2001
- [j2]Jason Cong, David Zhigang Pan:
Interconnect performance estimation models for design planning. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20(6): 739-752 (2001) - [j1]Jason Cong, Lei He, Cheng-Kok Koh, David Zhigang Pan:
Interconnect sizing and spacing with consideration of couplingcapacitance. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20(9): 1164-1169 (2001) - [c6]Jason Cong, David Zhigang Pan, Prasanna V. Srinivas:
Improved crosstalk modeling for noise constrained interconnect optimization. ASP-DAC 2001: 373-378
1990 – 1999
- 1999
- [c5]Jason Cong, David Zhigang Pan:
Interconnect Delay Estimation Models for Synthesis and Design Planning. ASP-DAC 1999: 97-100 - [c4]Jason Cong, David Zhigang Pan:
Interconnect Estimation and Dlanning for Deep Submicron Designs. DAC 1999: 507-510 - [c3]Jason Cong, Tianming Kong, David Zhigang Pan:
Buffer block planning for interconnect-driven floorplanning. ICCAD 1999: 358-363 - 1997
- [c2]Jason Cong, David Zhigang Pan, Lei He, Cheng-Kok Koh, Kei-Yong Khoo:
Interconnect design for deep submicron ICs. ICCAD 1997: 478-485 - [c1]Jason Cong, Lei He, Cheng-Kok Koh, David Zhigang Pan:
Global interconnect sizing and spacing with consideration of coupling capacitance. ICCAD 1997: 628-633
Coauthor Index
[i71] [c281] [c278] [c275] [i67] [i65] [i55] [j107] [j106] [c273] [c272] [c266] [c265] [i52] [i51] [i50] [i49] [i46] [i45] [i44] [j98] [c262] [c259] [c258] [c257] [c256] [c255] [c253] [c252] [c250] [c246] [c244] [i42] [i41] [i40] [i38] [i36] [i34] [i33] [j94] [j93] [c243] [c236] [c235] [c234] [c231] [c227] [i32] [i31] [i30] [i27] [i26] [i25] [i24] [i23] [i22] [i21] [j82] [c224] [c222] [c219] [c218] [c217] [c212] [i19] [i18] [c182]
[j114] [j108] [i48] [j101] [j99] [c255] [c245] [j97] [j96] [j95] [j94] [j92] [c242] [c237] [j91] [j84] [j82] [c226] [c225] [c216] [c212] [c211] [j78] [j77] [c207] [c206] [c204] [c203] [c197] [c196] [c195] [c194] [c193] [c186] [c185] [c183] [c181] [c180] [j67] [j66] [j65] [j64] [c179] [c178] [c171] [c168] [i17] [i16] [j60] [j58] [j56] [j55] [c162] [c156] [c154] [c152] [j52] [c150] [c146] [c142] [j43] [c135] [c132] [c126]
Haoxing Ren
aka: Haoxing Mark Ren
aka: Haoxing Mark Ren
[j111] [c280] [i61] [i57] [i56] [j99] [i39] [j92] [j83] [i20] [j80] [j79] [j78] [c207] [c201] [j71] [j66] [j65] [j61] [c178] [c175] [c172] [i16] [j60] [j57] [j56] [j55] [j54] [c152] [j52] [j48] [j47] [c150] [c149] [c148] [c146] [c144] [c141] [r3] [j46] [j44] [j43] [c138] [c137] [c136] [c135] [c132] [c131] [c129] [c128] [c126] [i14] [c124] [c122] [c121] [c118] [i13] [i12] [i11] [i10] [i9] [i8] [i7] [i6] [i5] [i4] [i3] [i2] [i1] [j33] [c116] [c115] [c113] [c111] [c110] [j30] [c106] [c105] [c101] [c99] [c95] [c86]
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last updated on 2025-05-19 21:09 CEST by the dblp team
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