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ORCIDYale N. Patt
Person information
- affiliation: University of Texas at Austin, USA
- award (2016): Benjamin Franklin Medal
- award (2013): Harry H. Goode Memorial Award
- award (1999): W. Wallace McDowell Award
- award (1996): Eckert-Mauchly Award
- award (1995): IEEE Emanuel R. Piore Award
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2020 – today
- 2024
[j53]Yale N. Patt
:
The CORRECT First Course in Computing for Serious Students. Computer 57(4): 108-112 (2024)- [c155]Yale N. Patt:
HCW 2024 Keynote: Hetero: Where we've been, Where we are, and What Next? IPDPS (Workshops) 2024: 5 - [c154]Yale N. Patt:
Hetero: Where we've been, Where we are, and What Next? IPDPS (Workshops) 2024: 5 - [c153]Aniket Anand Deshmukh, Lingzhe Chester Cai, Yale N. Patt:
Alternate Path Fetch. ISCA 2024: 1217-1229 - [c152]Aniket Anand Deshmukh, Lingzhe Chester Cai, Yale N. Patt:
Timely, Efficient, and Accurate Branch Precomputation. MICRO 2024: 480-492 - 2022
- [c151]Ali Fakhrzadehgan, Yale N. Patt, Prashant J. Nair, Moinuddin K. Qureshi:
SafeGuard: Reducing the Security Risk from Row-Hammer via Low-Cost Integrity Protection. HPCA 2022: 373-386 - 2021
- [c150]Aniket Anand Deshmukh, Yale N. Patt:
Criticality Driven Fetch. MICRO 2021: 380-391 - [c149]Stephen Pruett, Yale N. Patt:
Branch Runahead: An Alternative to Branch Prediction for Impossible to Predict Branches. MICRO 2021: 804-815 - 2020
- [c148]Faruk Guvenilir, Yale N. Patt:
Tailored Page Sizes. ISCA 2020: 900-912 - [c147]Siavash Zangeneh, Stephen Pruett, Sangkug Lym, Yale N. Patt:
BranchNet: A Convolutional Neural Network to Predict Hard-To-Predict Branches. MICRO 2020: 118-130 - [i1]Stephen Pruett, Yale N. Patt:
Dynamic Merge Point Prediction. CoRR abs/2005.14691 (2020)
2010 – 2019
- 2018
- [c146]Ben Lin, Michael B. Healy, Rustam Miftakhutdinov, Philip G. Emma, Yale N. Patt:
Duplicon Cache: Mitigating Off-Chip Memory Bank and Bank Group Conflicts Via Data Duplication. MICRO 2018: 285-297 - 2017
- [e5]Yale N. Patt, S. K. Nandy:
2017 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation, SAMOS 2017, Pythagorion, Greece, July 17-20, 2017. IEEE 2017, ISBN 978-1-5386-3437-0 [contents] - 2016
- [j52]Milad Hashemi, Debbie Marr, Doug Carmean, Yale N. Patt:
Efficient Execution of Bursty Applications. IEEE Comput. Archit. Lett. 15(2): 85-88 (2016) - [j51]Onur Mutlu, Rich Belgard, Thomas R. Gross, Norman P. Jouppi, John L. Hennessy, Steven A. Przybylski, Chris Rowen, Yale N. Patt, Wen-mei W. Hwu, Stephen W. Melvin, Michael Shebanow, Tse-Yu Yeh, Andy Wolfe:
Common Bonds: MIPS, HPS, Two-Level Branch Prediction, and Compressed Code RISC Processor. IEEE Micro 36(4): 70-85 (2016) - [c145]Yale N. Patt:
Greater Performance and Better Efficiency: Predicated Execution has shown us the way. PACT 2016: 151 - [c144]Milad Hashemi, Khubaib, Eiman Ebrahimi, Onur Mutlu, Yale N. Patt:
Accelerating Dependent Cache Misses with an Enhanced Memory Controller. ISCA 2016: 444-455 - [c143]Milad Hashemi, Onur Mutlu, Yale N. Patt:
Continuous runahead: Transparent hardware acceleration for memory intensive workloads. MICRO 2016: 61:1-61:12 - 2015
- [c142]Milad Hashemi, Yale N. Patt:
Filtered runahead execution with a runahead buffer. MICRO 2015: 358-369 - 2014
- [c141]Tse-Yu Yeh, Deborah T. Marr, Yale N. Patt:
Author retrospective for increasing the instruction fetch rate via multiple branch prediction and a branch address cache. ICS 25th Anniversary 2014: 24-25 - 2013
- [c140]José A. Joao, M. Aater Suleman, Onur Mutlu, Yale N. Patt:
Utility-based acceleration of multithreaded applications on asymmetric CMPs. ISCA 2013: 154-165 - [c139]Sani R. Nassif, Yale N. Patt, Magdy S. Abadir:
Keynote 1 - VLSI 2.0: R&D Post Moore. VLSI-SoC 2013 - 2012
- [j50]Eiman Ebrahimi, Chang Joo Lee, Onur Mutlu, Yale N. Patt:
Fairness via Source Throttling: A Configurable and High-Performance Fairness Substrate for Multicore Memory Systems. ACM Trans. Comput. Syst. 30(2): 7:1-7:35 (2012) - [c138]José A. Joao, M. Aater Suleman, Onur Mutlu, Yale N. Patt:
Bottleneck identification and scheduling in multithreaded applications. ASPLOS 2012: 223-234 - [c137]Yale N. Patt:
High performance supercomputers: should the individual processor be more than a brick? ICS 2012: 1-2 - [c136]Rustam Miftakhutdinov, Eiman Ebrahimi, Yale N. Patt:
Predicting Performance Impact of DVFS for Realistic Memory Systems. MICRO 2012: 155-165 - [c135]Khubaib, M. Aater Suleman, Milad Hashemi, Chris Wilkerson, Yale N. Patt:
MorphCore: An Energy-Efficient Microarchitecture for High Performance ILP and High Throughput TLP. MICRO 2012: 305-316 - [c134]Marco A. Z. Alves, Khubaib, Eiman Ebrahimi, Veynu Narasiman, Carlos Villavieja, Philippe Olivier Alexandre Navaux, Yale N. Patt:
Energy Savings via Dead Sub-Block Prediction. SBAC-PAD 2012: 51-58 - 2011
- [j49]Yale N. Patt, Onur Mutlu:
Top Picks [Guest editors' introduction]. IEEE Micro 31(1): 6-10 (2011) - [j48]M. Aater Suleman, Onur Mutlu, José A. Joao, Khubaib, Yale N. Patt:
Data Marshaling for Multicore Systems. IEEE Micro 31(1): 56-64 (2011) - [j47]Chang Joo Lee, Onur Mutlu, Veynu Narasiman, Yale N. Patt:
Prefetch-Aware Memory Controllers. IEEE Trans. Computers 60(10): 1406-1430 (2011) - [c133]Eiman Ebrahimi, Chang Joo Lee, Onur Mutlu, Yale N. Patt:
Prefetch-aware shared resource management for multi-core systems. ISCA 2011: 141-152 - [c132]Veynu Narasiman, Michael Shebanow, Chang Joo Lee, Rustam Miftakhutdinov, Onur Mutlu, Yale N. Patt:
Improving GPU performance via large warps and two-level warp scheduling. MICRO 2011: 308-317 - [c131]Eiman Ebrahimi, Rustam Miftakhutdinov, Chris Fallin, Chang Joo Lee, José A. Joao, Onur Mutlu, Yale N. Patt:
Parallel application memory scheduling. MICRO 2011: 362-373 - [r1]Yale N. Patt:
HPS Microarchitecture. Encyclopedia of Parallel Computing 2011: 850-851 - 2010
- [j46]M. Aater Suleman, Onur Mutlu, Moinuddin K. Qureshi, Yale N. Patt:
Accelerating Critical Section Execution with Asymmetric Multicore Architectures. IEEE Micro 30(1): 60-70 (2010) - [c130]M. Aater Suleman, Moinuddin K. Qureshi, Khubaib, Yale N. Patt:
Feedback-directed pipeline parallelism. PACT 2010: 147-156 - [c129]Eiman Ebrahimi, Chang Joo Lee, Onur Mutlu, Yale N. Patt:
Fairness via source throttling: a configurable and high-performance fairness substrate for multi-core memory systems. ASPLOS 2010: 335-346 - [c128]M. Aater Suleman, Onur Mutlu, José A. Joao, Khubaib, Yale N. Patt:
Data marshaling for multi-core architectures. ISCA 2010: 441-450 - [e4]Yale N. Patt, Pierfrancesco Foglia, Evelyn Duesterwald, Paolo Faraboschi, Xavier Martorell:
High Performance Embedded Architectures and Compilers, 5th International Conference, HiPEAC 2010, Pisa, Italy, January 25-27, 2010. Proceedings. Lecture Notes in Computer Science 5952, Springer 2010, ISBN 978-3-642-11514-1 [contents]
2000 – 2009
- 2009
- [j45]Hyesoon Kim, José A. Joao, Onur Mutlu, Chang Joo Lee, Yale N. Patt, Robert Cohn:
Virtual Program Counter (VPC) Prediction: Very Low Cost Indirect Branch Prediction Using Conditional Branch Prediction Hardware. IEEE Trans. Computers 58(9): 1153-1170 (2009) - [c127]Yale N. Patt:
The Challenges of Multicore: Information and Mis-Information. ARCS 2009: 3 - [c126]M. Aater Suleman, Onur Mutlu, Moinuddin K. Qureshi, Yale N. Patt:
Accelerating critical section execution with asymmetric multi-core architectures. ASPLOS 2009: 253-264 - [c125]Eiman Ebrahimi, Onur Mutlu, Yale N. Patt:
Techniques for bandwidth-efficient prefetching of linked data structures in hybrid prefetching systems. HPCA 2009: 7-17 - [c124]Yale N. Patt:
Multi-core demands multi-interfaces. HPCA 2009: 147-148 - [c123]José A. Joao, Onur Mutlu, Yale N. Patt:
Flexible reference-counting-based hardware acceleration for garbage collection. ISCA 2009: 418-428 - [c122]Eiman Ebrahimi, Onur Mutlu, Chang Joo Lee, Yale N. Patt:
Coordinated control of multiple prefetchers in multi-core systems. MICRO 2009: 316-326 - [c121]Chang Joo Lee, Veynu Narasiman, Onur Mutlu, Yale N. Patt:
Improving memory bank-level parallelism in the presence of prefetching. MICRO 2009: 327-336 - [c120]Yale N. Patt:
Multi-core demands multi-interfaces. PPoPP 2009: 99-100 - [c119]Yale N. Patt:
What Else Is Broken? Can We Fix It? SAMOS 2009: 1 - 2008
- [j44]José A. Joao, Onur Mutlu, Hyesoon Kim, Yale N. Patt:
Dynamic Predication of Indirect Jumps. IEEE Comput. Archit. Lett. 7(1): 1-4 (2008) - [j43]Moinuddin K. Qureshi, Aamer Jaleel, Yale N. Patt, Simon C. Steely Jr., Joel S. Emer:
Set-Dueling-Controlled Adaptive Insertion for High-Performance Caching. IEEE Micro 28(1): 91-98 (2008) - [c118]José A. Joao, Onur Mutlu, Hyesoon Kim, Rishi Agarwal, Yale N. Patt:
Improving the performance of object-oriented languages with dynamic predication of indirect jumps. ASPLOS 2008: 80-90 - [c117]M. Aater Suleman, Moinuddin K. Qureshi, Yale N. Patt:
Feedback-driven threading: power-efficient and high-performance execution of multi-threaded workloads on CMPs. ASPLOS 2008: 277-286 - [c116]Chang Joo Lee, Hyesoon Kim, Onur Mutlu, Yale N. Patt:
Performance-aware speculation control using wrong path usefulness prediction. HPCA 2008: 39-49 - [c115]Francis Tseng, Yale N. Patt:
Achieving Out-of-Order Performance with Almost In-Order Complexity. ISCA 2008: 3-12 - [c114]Chang Joo Lee, Onur Mutlu, Veynu Narasiman, Yale N. Patt:
Prefetch-Aware DRAM Controllers. MICRO 2008: 200-209 - [c113]Yale N. Patt:
Can They Be Fixed: Some Thoughts After 40 Years in the Business. SAMOS 2008: 1 - 2007
- [j42]José A. Joao, Onur Mutlu, Hyesoon Kim, Yale N. Patt:
Dynamic Predication of Indirect Jumps. IEEE Comput. Archit. Lett. 6(2): 25-28 (2007) - [j41]Hyesoon Kim, José A. Joao, Onur Mutlu, Yale N. Patt:
Diverge-Merge Processor: Generalized and Energy-Efficient Dynamic Predication. IEEE Micro 27(1): 94-104 (2007) - [j40]Joel S. Emer, Mark D. Hill, Yale N. Patt, Joshua J. Yi, Derek Chiou, Resit Sendag:
Single-Threaded vs. Multithreaded: Where Should We Focus? IEEE Micro 27(6): 14-24 (2007) - [c112]Hyesoon Kim, José A. Joao, Onur Mutlu, Yale N. Patt:
Profile-assisted Compiler Support for Dynamic Predication in Diverge-Merge Processors. CGO 2007: 367-378 - [c111]Yale N. Patt:
The Transformation Hierarchy in the Era of Multi-core. HiPC 2007: 5 - [c110]Santhosh Srinath, Onur Mutlu, Hyesoon Kim, Yale N. Patt:
Feedback Directed Prefetching: Improving the Performance and Bandwidth-Efficiency of Hardware Prefetchers. HPCA 2007: 63-74 - [c109]Moinuddin K. Qureshi, M. Aater Suleman, Yale N. Patt:
Line Distillation: Increasing Cache Capacity by Filtering Unused Words in Cache Lines. HPCA 2007: 250-259 - [c108]Moinuddin K. Qureshi, Aamer Jaleel, Yale N. Patt, Simon C. Steely Jr., Joel S. Emer:
Adaptive insertion policies for high performance caching. ISCA 2007: 381-391 - [c107]Hyesoon Kim, José A. Joao, Onur Mutlu, Chang Joo Lee, Yale N. Patt, Robert Cohn:
VPC prediction: reducing the cost of indirect branches via hardware-based dynamic devirtualization. ISCA 2007: 424-435 - 2006
- [j39]Jean-Luc Gaudiot, Yale N. Patt, Kevin Skadron:
Foreword. IEEE Comput. Archit. Lett. 5(2) (2006) - [j38]Onur Mutlu, Hyesoon Kim, Yale N. Patt:
Efficient Runahead Execution: Power-Efficient Memory Latency Tolerance. IEEE Micro 26(1): 10-20 (2006) - [j37]Hyesoon Kim, Onur Mutlu, Yale N. Patt, Jared Stark:
Wish Branches: Enabling Adaptive and Aggressive Predicated Execution. IEEE Micro 26(1): 48-58 (2006) - [j36]Onur Mutlu, Hyesoon Kim, Yale N. Patt:
Address-Value Delta (AVD) Prediction: A Hardware Technique for Efficiently Parallelizing Dependent Cache Misses. IEEE Trans. Computers 55(12): 1491-1508 (2006) - [c106]Hyesoon Kim, M. Aater Suleman, Onur Mutlu, Yale N. Patt:
2D-Profiling: Detecting Input-Dependent Branches with a Single Input Data Set. CGO 2006: 159-172 - [c105]Yale N. Patt:
Computer Architecture Research and Future Microprocessors: Where Do We Go from Here? ISCA 2006: 2 - [c104]Moinuddin K. Qureshi, Daniel N. Lynch, Onur Mutlu, Yale N. Patt:
A Case for MLP-Aware Cache Replacement. ISCA 2006: 167-178 - [c103]Hyesoon Kim, José A. Joao, Onur Mutlu, Yale N. Patt:
Diverge-Merge Processor (DMP): Dynamic Predicated Execution of Complex Control-Flow Graphs Based on Frequently Executed Paths. MICRO 2006: 53-64 - [c102]Moinuddin K. Qureshi, Yale N. Patt:
Utility-Based Cache Partitioning: A Low-Overhead, High-Performance, Runtime Mechanism to Partition Shared Caches. MICRO 2006: 423-432 - 2005
- [j35]Onur Mutlu, Hyesoon Kim, Jared Stark, Yale N. Patt:
On Reusing the Results of Pre-Executed Instructions in a Runahead Execution Processor. IEEE Comput. Archit. Lett. 4(1): 2 (2005) - [j34]Onur Mutlu, Hyesoon Kim, David N. Armstrong, Yale N. Patt:
Using the First-Level Caches as Filters to Reduce the Pollution Caused by Speculative Memory References. Int. J. Parallel Program. 33(5): 529-559 (2005) - [j33]Onur Mutlu, Hyesoon Kim, David N. Armstrong, Yale N. Patt:
An Analysis of the Performance Impact of Wrong-Path Memory References on Out-of-Order and Runahead Execution Processors. IEEE Trans. Computers 54(12): 1556-1571 (2005) - [c101]Yale N. Patt:
The microprocessor of the year 2014: do Pentium 4, Pentium M, and Power 5 provide any hints? AICCSA 2005: 1 - [c100]Moinuddin K. Qureshi, Onur Mutlu, Yale N. Patt:
Microarchitecture-Based Introspection: A Technique for Transient-Fault Tolerance in Microprocessors. DSN 2005: 434-443 - [c99]Yale N. Patt:
A Unifying Theory of Distributed Processing (Or, The Chutzpah One Should Expect When You Invite a Microarchitect into Your Sandbox). IPDPS 2005 - [c98]Onur Mutlu, Hyesoon Kim, Yale N. Patt:
Techniques for Efficient Processing in Runahead Execution Engines. ISCA 2005: 370-381 - [c97]Moinuddin K. Qureshi, David Thompson, Yale N. Patt:
The V-Way Cache: Demand Based Associativity via Global Replacement. ISCA 2005: 544-555 - [c96]Hyesoon Kim, Onur Mutlu, Jared Stark, Yale N. Patt:
Wish Branches: Combining Conditional Branching and Predication for Adaptive Predicated Execution. MICRO 2005: 43-54 - [c95]Onur Mutlu, Hyesoon Kim, Yale N. Patt:
Address-Value Delta (AVD) Prediction: Increasing the Effectiveness of Runahead Execution by Exploiting Regular Memory Allocation Patterns. MICRO 2005: 233-244 - 2004
- [b1]Yale N. Patt, Sanjay J. Patel:
Introduction to computing systems - from bits and gates to C and beyond (2. ed.). McGraw-Hill 2004, ISBN 978-0-07-246750-5, pp. I-XXIV, 1-632 - [c94]Yale N. Patt:
Opening and keynote 1. ISPASS 2004: 1 - [c93]Brad Calder, Daniel Citron, Yale N. Patt, James E. Smith:
The future of simulation: A field of dreams. ISPASS 2004: 169 - [c92]David N. Armstrong, Hyesoon Kim, Onur Mutlu, Yale N. Patt:
Wrong Path Events: Exploiting Unusual and Illegal Program Behavior for Early Misprediction Detection and Recovery. MICRO 2004: 119-128 - [c91]Onur Mutlu, Hyesoon Kim, David N. Armstrong, Yale N. Patt:
Cache Filtering Techniques to Reduce the Negative Impact of Useless Speculative Memory References on Processor Performance. SBAC-PAD 2004: 2-9 - [c90]Onur Mutlu, Hyesoon Kim, David N. Armstrong, Yale N. Patt:
Understanding the effects of wrong-path memory references on processor performance. WMPI 2004: 56-64 - 2003
- [j32]Onur Mutlu, Jared Stark, Chris Wilkerson, Yale N. Patt:
Runahead Execution: An Effective Alternative to Large Instruction Windows. IEEE Micro 23(6): 20-25 (2003) - [c89]Yale N. Patt:
The High Performance Microprocessor in the Year 2013: What Will It Look Like? What It Won't Look Like? HiPC 2003: 105 - [c88]Onur Mutlu, Jared Stark, Chris Wilkerson, Yale N. Patt:
Runahead Execution: An Alternative to Very Large Instruction Windows for Out-of-Order Processors. HPCA 2003: 129-140 - [c87]Paul Racunas, Yale N. Patt:
Partitioned first-level cache design for clustered microarchitectures. ICS 2003: 22-31 - [c86]Yale N. Patt:
Teaching and teaching computer architecture: two very different topics: (some opinions about each). WCAE 2003: 2 - 2002
- [c85]Stephen W. Melvin, Yale N. Patt:
Handling of packet dependencies: a critical issue for highly parallel network processors. CASES 2002: 202-209 - [c84]Mary D. Brown, Yale N. Patt:
Using Internal Redundant Representations and Limited Bypass to Support Pipelined Adders and Register Files. HPCA 2002: 289-298 - [c83]Robert S. Chappell, Francis Tseng, Yale N. Patt, Adi Yoaz:
Difficult-Path Branch Prediction Using Subordinate Microthreads. ISCA 2002: 307-317 - [c82]Robert S. Chappell, Francis Tseng, Adi Yoaz, Yale N. Patt:
Microarchitectural support for precomputation microthreads. MICRO 2002: 74-84 - [e3]Yale N. Patt, Dirk Grunwald, Kevin Skadron:
29th International Symposium on Computer Architecture (ISCA 2002), 25-29 May 2002, Anchorage, AK, USA. IEEE Computer Society 2002, ISBN 0-7695-1605-X [contents] - 2001
- [j31]Yale N. Patt:
Requirements, bottlenecks, and good fortune: agents for microprocessor evolution. Proc. IEEE 89(11): 1553-1559 (2001) - [c81]Mary D. Brown, Jared Stark, Yale N. Patt:
Select-free instruction scheduling logic. MICRO 2001: 204-213 - [c80]Judith L. Gersting, Peter B. Henderson, Philip Machanick, Yale N. Patt:
Programming early considered harmful. SIGCSE 2001: 402-403 - [e2]Yale N. Patt, Josh Fisher, Paolo Faraboschi, Kevin Skadron:
Proceedings of the 34th Annual International Symposium on Microarchitecture, Austin, Texas, USA, December 1-5, 2001. ACM/IEEE Computer Society 2001, ISBN 0-7695-1369-7 [contents] - 2000
- [j30]Gregory R. Ganger, Marshall K. McKusick, Craig A. N. Soules, Yale N. Patt:
Soft updates: a solution to the metadata update problem in file systems. ACM Trans. Comput. Syst. 18(2): 127-153 (2000) - [c79]Yale N. Patt:
Higher and Higher Performance Microprocessors: Are The Problems Just Too Hard To Solve? EUROMICRO 2000: 1015 - [c78]Jared Stark, Mary D. Brown, Yale N. Patt:
On pipelining dynamic instruction scheduling logic. MICRO 2000: 57-66
1990 – 1999
- 1999
- [j29]Sanjay J. Patel, Daniel H. Friendly, Yale N. Patt:
Evaluation of Design Options for the Trace Cache Fetch Mechanism. IEEE Trans. Computers 48(2): 193-204 (1999) - [c77]Robert S. Chappell, Jared Stark, Sangwook P. Kim, Steven K. Reinhardt, Yale N. Patt:
Simultaneous Subordinate Microthreading (SSMT). ISCA 1999: 186-195 - [c76]Yale N. Patt:
Computer architecture education: mechanical engineers need it too. WCAE@HPCA 1999: 1 - 1998
- [j28]Eric Hao, Po-Yung Chang, Marius Evers, Yale N. Patt:
Increasing the Instruction Fetch Rate via Block-Structured Instruction Set Architectures. Int. J. Parallel Program. 26(4): 449-478 (1998) - [j27]Gregory R. Ganger, Yale N. Patt:
Using System-Level Models to Evaluate I/O Subsystem Designs. IEEE Trans. Computers 47(6): 667-678 (1998) - [c75]Jared Stark, Marius Evers, Yale N. Patt:
Variable Length Path Branch Prediction. ASPLOS 1998: 170-179 - [c74]