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ORCIDS. Ramesh 0001
Person information
- affiliation: Indian Institute of Technology, Bombay, Mumbai, India
Other persons with the same name
- S. Ramesh (aka: Ramesh S.) — disambiguation page
- S. Ramesh 0002
![[0000-0002-8501-7447]](https://dblp.dagstuhl.de/img/orcid-mark.12x12.png "0000-0002-8501-7447")
(aka: Ramesh S. 0002, Sethu Ramesh) — General Motors R&D, India Science Lab, Bangalore, India - S. Ramesh 0003 (aka: Ramesh Sekaran) — Velagapudi Ramakrishna Siddhartha Engineering College, Vijayawada, India (and 2 more)
- S. Ramesh 0004 (aka: Shiva Ramesh 0004) — LSI Logic Corporation, Milpitas, CA, USA
- S. Ramesh 0005 (aka: Ramesh Sundar) — Vignan Foundation for Science, Technology & Research, Guntur, India
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Journal Articles
- 2006
[j11]Mangala Gowri Nanda, S. Ramesh:
Interprocedural slicing of multithreaded programs with applications to Java. ACM Trans. Program. Lang. Syst. 28(6): 1088-1144 (2006)- 2003
- [j10]Babita Sharma, S. D. Dhodapkar, S. Ramesh:
Assertion checking environment (ACE) for formal verification of C programs. Reliab. Eng. Syst. Saf. 81(3): 281-290 (2003) - 2001
- [j9]Partha S. Roop, Arcot Sowmya, S. Ramesh:
Forced simulation: A technique for automating component reuse in embedded systems. ACM Trans. Design Autom. Electr. Syst. 6(4): 602-628 (2001) - [j8]Sridhar Iyer, S. Ramesh:
Apportioning: A Technique for Efficient Reachability Analysis of Concurrent Object-Oriented Programs. IEEE Trans. Software Eng. 27(11): 1037-1056 (2001) - 1999
- [j7]S. Ramesh:
Implementation of communicating reactive processes. Parallel Comput. 25(6): 703-727 (1999) - 1998
- [j6]S. Ramesh, Chandrashekar M. Shetty:
Impossibility of Synchronization in the Presence of Preemption. Parallel Process. Lett. 8(1): 111-120 (1998) - [j5]Arcot Sowmya, S. Ramesh:
Extending Statecharts with Temporal Logic. IEEE Trans. Software Eng. 24(3): 216-231 (1998) - 1996
- [j4]S. Ramesh, Bommadevara N. Srinivas:
A Direct Characterization of Completion. Theor. Comput. Sci. 154(2): 379-385 (1996) - 1992
- [j3]Jozef Hooman, S. Ramesh, Willem P. de Roever:
A Compositional Axiomatization of Statecharts. Theor. Comput. Sci. 101(2): 289-335 (1992) - 1990
- [j2]S. Ramesh:
On the Completeness of Modular Proof Systems. Inf. Process. Lett. 36(4): 195-201 (1990) - 1983
- [j1]S. Ramesh, S. L. Mehndiratta:
The Liveness Property of On-the-Fly Garbage Collector - A Proof. Inf. Process. Lett. 17(4): 189-195 (1983)
Conference and Workshop Papers
- 2007
- [c24]Ajith K. John, Babita Sharma, A. K. Bhattacharjee, S. D. Dhodapkar, S. Ramesh:
Detection of Runtime Errors in MISRA C Programs: A Deductive Approach. SAFECOMP 2007: 491-504 - 2004
- [c23]Vijay D'Silva, S. Ramesh, Arcot Sowmya:
Synchronous Protocol Automata: A Framework for Modelling and Verification of SoC Communication Architectures. DATE 2004: 390-395 - [c22]Ambar A. Gadkari, S. Ramesh, Rubin A. Parekhji:
CESC: a visual formalism for specification and verification of SoCs. ACM Great Lakes Symposium on VLSI 2004: 354-357 - [c21]S. Ramesh, Aditya Rajeev Kulkarni, Viraj Kamat:
Slicing tools for synchronous reactive programs. ISSTA 2004: 217-220 - [c20]Vijay D'Silva, S. Ramesh, Arcot Sowmya:
Bridge Over Troubled Wrappers: Automated Interface Synthesis. VLSI Design 2004: 189-194 - 2003
- [c19]Mangala Gowri Nanda, S. Ramesh:
Pointer Analysis of Multithreaded Java Programs. SAC 2003: 1068-1075 - [c18]Asif Iqbal, A. K. Bhattacharjee, S. D. Dhodapkar, S. Ramesh:
Visual Modeling and Verification of Distributed Reactive Systems. SAFECOMP 2003: 22-34 - [c17]Aditya Rajeev Kulkarni, S. Ramesh:
Static Slicing of Reactive Programs. SCAM 2003: 98-107 - 2002
- [c16]Partha S. Roop, Arcot Sowmya, S. Ramesh:
k-time Forced Simulation: A Formal Verification Technique for IP Reuse. ICCD 2002: 50-55 - [c15]Babita Sharma, S. D. Dhodapkar, S. Ramesh:
Assertion Checking Environment (ACE) for Formal Verification of C Programs. SAFECOMP 2002: 284-295 - [c14]Vinod Ganapathy, S. Ramesh:
Slicing Synchronous Reactive Programs. SLAP@ETAPS 2002: 50-64 - 2001
- [c13]Partha S. Roop, Arcot Sowmya, S. Ramesh:
A formal approach to component based development of synchronous programs. ASP-DAC 2001: 421-424 - 2000
- [c12]Partha S. Roop, Arcot Sowmya, S. Ramesh:
Automated Component Adaptation by Forced Simulation. ACAC 2000: 74-81 - [c11]Mangala Gowri Nanda, S. Ramesh:
Slicing concurrent programs. ISSTA 2000: 180-190 - [c10]Partha S. Roop, Arcot Sowmya, S. Ramesh:
Automatic Component Matching Using Forced Simulation. VLSI Design 2000: 64-69 - 1999
- [c9]S. Ramesh, Purandar Bhaduri:
Validation of Pipelined Processor Designs Using Esterel Tools: A Case Study. CAV 1999: 84-95 - 1998
- [c8]Sridhar Iyer, S. Ramesh:
Apportioning: a technique for efficient reachability analysis of concurrent object-oriented programs. HiPC 1998: 124-131 - 1997
- [c7]Sridhar Iyer, S. Ramesh:
A Tool-Suite for Reachability Analysis of Concurrent Object-Oriented Programs. APSEC 1997: 160- - [c6]Sameer Mahajan, S. Ramesh:
Concurrent Logic Programming and pi Calculus. ICLP 1997: 411 - 1993
- [c5]Gérard Berry, S. Ramesh, R. K. Shyamasundar:
Communicating Reactive Processes. POPL 1993: 85-98 - 1992
- [c4]S. Ramesh:
Fully Abstract Semantics for Higher Order Communicating Systems. MFCS 1992: 463-471 - 1987
- [c3]S. Ramesh:
A New Efficient Implementation of CSP with Output Guards. ICDCS 1987: 266-273 - [c2]S. Ramesh:
A New and Efficient Implementation of Multiprocess Synchronization. PARLE (2) 1987: 387-401 - 1985
- [c1]S. Ramesh, S. L. Mehndiratta:
A New Class of High Level Programs for Distributed Computing Systems. FSTTCS 1985: 42-72
Coauthor Index
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