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ORCIDSachin S. Sapatnekar
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- affiliation: University of Minnesota, USA
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2020 – today
- 2024
[j136]Vidya A. Chhabria
, Wenjing Jiang, Andrew B. Kahng, Sachin S. Sapatnekar:
A Machine Learning Approach to Improving Timing Consistency between Global Route and Detailed Route. ACM Trans. Design Autom. Electr. Syst. 29(1): 18:1-18:25 (2024)- [c263]Kishor Kunal, Jitesh Poojary, S. Ramprasath, Ramesh Harjani, Sachin S. Sapatnekar:
Automated synthesis of mixed-signal ML inference hardware under accuracy constraints. ASPDAC 2024: 478-483 - [c262]Kishor Kunal, Meghna Madhusudan, Jitesh Poojary, S. Ramprasath, Arvind K. Sharma, Ramesh Harjani, Sachin S. Sapatnekar:
Reinforcing the Connection between Analog Design and EDA (Invited Paper). ASPDAC 2024: 665-670 - [c261]Zamshed I. Chowdhury, Hüsrev Cilasun, Salonik Resch, Masoud Zabihi, Yang Lv, Brandon Zink, Jian-Ping Wang, Sachin S. Sapatnekar, Ulya R. Karpuzcu:
On Gate Flip Errors in Computing-In-Memory. DATE 2024: 1-6 - [c260]Chetan Choppali Sudarshan, Nikhil Matkar, Sarma B. K. Vrudhula, Sachin S. Sapatnekar, Vidya A. Chhabria:
ECO-CHIP: Estimation of Carbon Footprint of Chiplet-based Architectures for Sustainable VLSI. HPCA 2024: 671-685 - [c259]Hüsrev Cilasun, Salonik Resch, Zamshed I. Chowdhury, Masoud Zabihi, Yang Lv, Brandon Zink, Jianping Wang, Sachin S. Sapatnekar, Ulya R. Karpuzcu:
On Error Correction for Nonvolatile Processing-In-Memory. ISCA 2024: 678-692 - [c258]Sudipta Mondal, Sachin S. Sapatnekar:
Hardware Acceleration of Inference on Dynamic GNNs. ISLPED 2024: 1-6 - [c257]Shiyu Guo, Sachin S. Sapatnekar, Jie Gu:
2.5 A 28nm Physical-Based Ray-Tracing Rendering Processor for Photorealistic Augmented Reality with Inverse Rendering and Background Clustering for Mobile Devices. ISSCC 2024: 44-46 - [c256]Wenjing Jiang, Vidya A. Chhabria, Sachin S. Sapatnekar:
IR-Aware ECO Timing Optimization Using Reinforcement Learning. MLCAD 2024: 7:1-7:7 - [c255]Shiyu Guo, Sachin S. Sapatnekar, Jie Gu:
Software-Hardware Codesign of Ray-Tracing Accelerator for Edge AR/VR With Viewpoint-Focused 3D Construction and Efficient Data Structure. MWSCAS 2024: 267-271 - [c254]Vidya A. Chhabria, Wenjing Jiang, Andrew B. Kahng, Rongjian Liang, Haoxing Ren, Sachin S. Sapatnekar, Bing-Yue Wu:
OpenROAD and CircuitOps: Infrastructure for ML EDA Research and Education. VTS 2024: 1-4 - [d1]Hüsrev Cilasun, William Moy, Ziqing Zeng, Tahmida Islam, Hao Lo, Alex Vanasse, Megan Tan, Mohammad Anees, Ramprasath S, Abhimanyu Kumar, Sachin S. Sapatnekar, Chris H. Kim, Ulya R. Karpuzcu:
COBI: A Coupled Oscillator Based Ising Chip for Combinatorial Optimization. Zenodo, 2024
- [i27]Vidya A. Chhabria, Wenjing Jiang, Sachin S. Sapatnekar:
IR-Aware ECO Timing Optimization Using Reinforcement Learning. CoRR abs/2402.07781 (2024) - 2023
- [j135]Nibedita Karmokar, Arvind K. Sharma, Jitesh Poojary, Meghna Madhusudan, Ramesh Harjani, Sachin S. Sapatnekar:
Constructive Placement and Routing for Common-Centroid Capacitor Arrays in Binary-Weighted and Split DACs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(9): 2782-2795 (2023) - [j134]Kishor Kunal, Tonmoy Dhar, Meghna Madhusudan, Jitesh Poojary, Arvind K. Sharma, Wenbin Xu, Steven M. Burns, Jiang Hu, Ramesh Harjani, Sachin S. Sapatnekar:
GNN-Based Hierarchical Annotation for Analog Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(9): 2801-2814 (2023) - [j133]Sudipta Mondal, Susmita Dey Manasi, Kishor Kunal, Ramprasath S, Ziqing Zeng, Sachin S. Sapatnekar:
A Unified Engine for Accelerating GNN Weighting/Aggregation Operations, With Efficient Load Balancing and Graph-Specific Caching. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(12): 4844-4857 (2023) - [j132]Vidya A. Chhabria, Vipul Ahuja, Ashwath Prabhu, Nikhil Patil, Palkesh Jain, Sachin S. Sapatnekar:
Encoder-Decoder Networks for Analyzing Thermal and Power Delivery Networks. ACM Trans. Design Autom. Electr. Syst. 28(1): 3:1-3:27 (2023) - [j131]Yaguang Li, Yishuang Lin, Meghna Madhusudan, Arvind K. Sharma, Sachin S. Sapatnekar, Ramesh Harjani, Jiang Hu:
Performance-driven Wire Sizing for Analog Integrated Circuits. ACM Trans. Design Autom. Electr. Syst. 28(2): 19:1-19:23 (2023) - [j130]Ramprasath Srinivasa Gopalakrishnan, Meghna Madhusudan, Arvind K. Sharma, Jitesh Poojary, Soner Yaldiz, Ramesh Harjani, Steven M. Burns, Sachin S. Sapatnekar:
A Generalized Methodology for Well Island Generation and Well-tap Insertion in Analog/Mixed-signal Layouts. ACM Trans. Design Autom. Electr. Syst. 28(5): 69:1-69:25 (2023) - [c253]Susmita Dey Manasi, Suvadeep Banerjee, Abhijit Davare, Anton A. Sorokin, Steven M. Burns, Desmond A. Kirkpatrick, Sachin S. Sapatnekar:
Reusing GEMM Hardware for Efficient Execution of Depthwise Separable Convolution on ASIC-Based DNN Accelerators. ASP-DAC 2023: 475-482 - [c252]Sumanth Kamineni, Arvind K. Sharma, Ramesh Harjani, Sachin S. Sapatnekar, Benton H. Calhoun:
AuxcellGen: A Framework for Autonomous Generation of Analog and Memory Unit Cells. DATE 2023: 1-6 - [c251]Nibedita Karmokar, Ramesh Harjani, Sachin S. Sapatnekar:
Minimum Unit Capacitance Calculation for Binary-Weighted Capacitor Arrays. DATE 2023: 1-2 - [c250]Ziqing Zeng, Sachin S. Sapatnekar:
Energy-efficient Hardware Acceleration of Shallow Machine Learning Applications. DATE 2023: 1-6 - [c249]Meghna Madhusudan, Jitesh Poojary, Arvind K. Sharma, Ramprasath S, Kishor Kunal, Sachin S. Sapatnekar, Ramesh Harjani:
Understanding Distance-Dependent Variations for Analog Circuits in a FinFET Technology. ESSDERC 2023: 69-72 - [c248]Mohammad Abdullah Al Shohel, Vidya A. Chhabria, Nestoras E. Evmorfopoulos, Sachin S. Sapatnekar:
Frequency-Domain Transient Electromigration Analysis Using Circuit Theory. ICCAD 2023: 1-8 - [c247]Salonik Resch, Hüsrev Cilasun, Masoud Zabihi, Zamshed Iqbal Chowdhury, Zhengyang Zhao, Jian-Ping Wang, Sachin S. Sapatnekar, Ulya R. Karpuzcu:
PimCity: A Compute in Memory Substrate featuring both Row and Column Parallel Computing. ICRC 2023: 1-10 - [c246]Salonik Resch, M. Hüsrev Cilasun, Zamshed I. Chowdhury, Masoud Zabihi, Zhengyang Zhao, Jian-Ping Wang, Sachin S. Sapatnekar, Ulya R. Karpuzcu:
On Endurance of Processing in (Nonvolatile) Memory. ISCA 2023: 79:1-79:13 - [c245]Sudipta Mondal, Ramprasath S, Ziqing Zeng, Kishor Kunal, Sachin S. Sapatnekar:
A Multicore GNN Training Accelerator. ISLPED 2023: 1-6 - [c244]Sachin S. Sapatnekar:
The ALIGN Automated Analog Layout Engine: Progress, Learnings, and Open Issues. ISPD 2023: 101-102 - [c243]Nestor E. Evmorfopoulos, Mohammad Abdullah Al Shohel, Olympia Axelou, Pavlos Stoikos, Vidya A. Chhabria, Sachin S. Sapatnekar:
Recent Progress in the Analysis of Electromigration and Stress Migration in Large Multisegment Interconnects. ISPD 2023: 115-123 - [c242]Vidya A. Chhabria, Sachin S. Sapatnekar:
Analysis of Pattern-dependent Rapid Thermal Annealing Effects on SRAM Design. ISQED 2023: 1-7 - [c241]Yishuang Lin, Yaguang Li, Meghna Madhusudan, Sachin S. Sapatnekar, Ramesh Harjani, Jiang Hu:
MMM: Machine Learning-Based Macro-Modeling for Linear Analog ICs and ADC/DACs. MLCAD 2023: 1-6 - [i26]Vidya A. Chhabria, Wenjing Jiang, Andrew B. Kahng, Sachin S. Sapatnekar:
A Machine Learning Approach to Improving Timing Consistency between Global Route and Detailed Route. CoRR abs/2305.06917 (2023) - [i25]Vidya A. Chhabria, Chetan Choppali Sudarshan, Sarma B. K. Vrudhula, Sachin S. Sapatnekar:
Towards Sustainable Computing: Assessing the Carbon Footprint of Heterogeneous Systems. CoRR abs/2306.09434 (2023) - [i24]Hadi Esmaeilzadeh, Soroush Ghodrati, Andrew B. Kahng, Sean Kinzer, Susmita Dey Manasi, Sachin S. Sapatnekar, Zhiang Wang:
Performance Analysis of DNN Inference/Training with Convolution and non-Convolution Operations. CoRR abs/2306.16767 (2023) - [i23]Hadi Esmaeilzadeh, Soroush Ghodrati, Andrew B. Kahng, Joon Kyung Kim, Sean Kinzer, Sayak Kundu, Rohan Mahapatra, Susmita Dey Manasi, Sachin S. Sapatnekar, Zhiang Wang, Ziqing Zeng:
An Open-Source ML-Based Full-Stack Optimization Framework for Machine Learning Accelerators. CoRR abs/2308.12120 (2023) - [i22]M. Hüsrev Cilasun, Ziqing Zeng, Ramprasath S, Abhimanyu Kumar, Hao Lo, William Cho, Chris H. Kim, Ulya R. Karpuzcu, Sachin S. Sapatnekar:
3SAT on an All-to-All-Connected CMOS Ising Solver Chip. CoRR abs/2309.11017 (2023) - [i21]Yang Lv, Brandon R. Zink, Robert P. Bloom, M. Hüsrev Cilasun, Pravin Khanal, Salonik Resch, Zamshed I. Chowdhury, Ali Habiboglu, Weigang Wang, Sachin S. Sapatnekar, Ulya R. Karpuczu, Jianping Wang:
Experimental demonstration of magnetic tunnel junction-based computational random-access memory. CoRR abs/2312.14264 (2023) - 2022
- [j129]Vidya A. Chhabria, Sachin S. Sapatnekar:
OpeNPDN: A Neural-Network-Based Framework for Power Delivery Network Synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(10): 3515-3528 (2022) - [j128]Salonik Resch, S. Karen Khatamifard, Zamshed I. Chowdhury, Masoud Zabihi, Zhengyang Zhao, M. Hüsrev Cilasun, Jianping Wang, Sachin S. Sapatnekar, Ulya R. Karpuzcu:
Energy-efficient and Reliable Inference in Nonvolatile Memory under Extreme Operating Conditions. ACM Trans. Embed. Comput. Syst. 21(5): 57:1-57:36 (2022) - [j127]Zamshed I. Chowdhury, S. Karen Khatamifard, Salonik Resch, M. Hüsrev Cilasun, Zhengyang Zhao, Masoud Zabihi, Meisam Razaviyayn, Jian-Ping Wang, Sachin S. Sapatnekar, Ulya R. Karpuzcu:
CRAM-Seq: Accelerating RNA-Seq Abundance Quantification Using Computational RAM. IEEE Trans. Emerg. Top. Comput. 10(4): 2055-2071 (2022) - [c240]Nibedita Karmokar, Meghna Madhusudan, Arvind K. Sharma, Ramesh Harjani, Mark Po-Hung Lin, Sachin S. Sapatnekar:
Common-Centroid Layout for Active and Passive Devices: A Review and the Road Ahead. ASP-DAC 2022: 114-121 - [c239]Sudipta Mondal, Susmita Dey Manasi, Kishor Kunal, Ramprasath S, Sachin S. Sapatnekar:
GNNIE: GNN inference engine with load-balancing and graph-specific caching. DAC 2022: 565-570 - [c238]Tonmoy Dhar, Ramprasath S, Jitesh Poojary, Soner Yaldiz, Steven M. Burns, Ramesh Harjani, Sachin S. Sapatnekar:
A Charge Flow Formulation for Guiding Analog/Mixed-Signal Placement. DATE 2022: 148-153 - [c237]Yishuang Lin, Yaguang Li, Donghao Fang, Meghna Madhusudan, Sachin S. Sapatnekar, Ramesh Harjani, Jiang Hu:
Are Analytical Techniques Worthwhile for Analog IC Placement? DATE 2022: 154-159 - [c236]Nibedita Karmokar, Arvind K. Sharma, Jitesh Poojary, Meghna Madhusudan, Ramesh Harjani, Sachin S. Sapatnekar:
Constructive Common-Centroid Placement and Routing for Binary-Weighted Capacitor Arrays. DATE 2022: 166-171 - [c235]Olympia Axelou, Nestor E. Evmorfopoulos, George Floros, George I. Stamoulis, Sachin S. Sapatnekar:
A Novel Semi-Analytical Approach for Fast Electromigration Stress Analysis in Multi-Segment Interconnects. ICCAD 2022: 27:1-27:7 - [c234]Sachin S. Sapatnekar:
EDAML 2022 Invited Speaker 7: Analog and Digital Circuit and Layout Optimization using Machine Learning. IPDPS Workshops 2022: 1188 - [c233]Ramprasath S, Meghna Madhusudan, Arvind K. Sharma, Jitesh Poojary, Soner Yaldiz, Ramesh Harjani, Steven M. Burns, Sachin S. Sapatnekar:
Analog/Mixed-Signal Layout Optimization using Optimal Well Taps. ISPD 2022: 159-166 - [c232]Vidya A. Chhabria, Wenjing Jiang, Andrew B. Kahng, Sachin S. Sapatnekar:
From Global Route to Detailed Route: ML for Fast and Accurate Wire Parasitics and Timing Prediction. MLCAD 2022: 7-14 - [c231]Hadi Esmaeilzadeh, Soroush Ghodrati, Andrew B. Kahng, Joon Kyung Kim, Sean Kinzer, Sayak Kundu, Rohan Mahapatra, Susmita Dey Manasi, Sachin S. Sapatnekar, Zhiang Wang, Ziqing Zeng:
Physically Accurate Learning-based Performance Prediction of Hardware-accelerated ML Algorithms. MLCAD 2022: 119-126 - [i20]M. Hüsrev Cilasun, Salonik Resch, Zamshed I. Chowdhury, Masoud Zabihi, Yang Lv, Brandon Zink, Jianping Wang, Sachin S. Sapatnekar, Ulya R. Karpuzcu:
Error Detection and Correction for Processing in Memory (PiM). CoRR abs/2207.13261 (2022) - 2021
- [j126]Tonmoy Dhar, Kishor Kunal, Yaguang Li, Meghna Madhusudan, Jitesh Poojary, Arvind K. Sharma, Wenbin Xu, Steven M. Burns, Ramesh Harjani, Jiang Hu, Desmond A. Kirkpatrick, Parijat Mukherjee, Soner Yaldiz, Sachin S. Sapatnekar:
ALIGN: A System for Automating Analog Layout. IEEE Des. Test 38(2): 8-18 (2021) - [j125]Luke R. Everson, Sachin S. Sapatnekar, Chris H. Kim:
A Time-Based Intra-Memory Computing Graph Processor Featuring A* Wavefront Expansion and 2-D Gradient Control. IEEE J. Solid State Circuits 56(7): 2281-2290 (2021) - [j124]M. Hüsrev Cilasun, Salonik Resch, Zamshed I. Chowdhury, Erin Olson, Masoud Zabihi, Zhengyang Zhao, Thomas Peterson, Keshab K. Parhi, Jianping Wang, Sachin S. Sapatnekar, Ulya R. Karpuzcu:
Spiking Neural Networks in Spintronic Computational RAM. ACM Trans. Archit. Code Optim. 18(4): 59:1-59:21 (2021) - [j123]Farhana Sharmin Snigdha, Susmita Dey Manasi, Jiang Hu, Sachin S. Sapatnekar:
SeFAct2: Selective Feature Activation for Energy-Efficient CNNs Using Optimized Thresholds. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40(7): 1423-1436 (2021) - [c230]Tonmoy Dhar, Jitesh Poojary, Yaguang Li, Kishor Kunal, Meghna Madhusudan, Arvind K. Sharma, Susmita Dey Manasi, Jiang Hu, Ramesh Harjani, Sachin S. Sapatnekar:
Fast and Efficient Constraint Evaluation of Analog Layout Using Machine Learning Models. ASP-DAC 2021: 158-163 - [c229]Susmita Dey Manasi, Sachin S. Sapatnekar:
DeepOpt: Optimized Scheduling of CNN Workloads for ASIC-based Systolic Deep Learning Accelerators. ASP-DAC 2021: 235-241 - [c228]Vidya A. Chhabria, Vipul Ahuja, Ashwath Prabhu, Nikhil Patil, Palkesh Jain, Sachin S. Sapatnekar:
Thermal and IR Drop Analysis Using Convolutional Encoder-Decoder Networks. ASP-DAC 2021: 690-696 - [c227]Mohammad Abdullah Al Shohel, Vidya A. Chhabria, Sachin S. Sapatnekar:
A New, Computationally Efficient "Blech Criterion" for Immortality in General Interconnects. DAC 2021: 913-918 - [c226]Arvind K. Sharma, Meghna Madhusudan, Steven M. Burns, Parijat Mukherjee, Soner Yaldiz, Ramesh Harjani, Sachin S. Sapatnekar:
Common-Centroid Layouts for Analog Circuits: Advantages and Limitations. DATE 2021: 1224-1229 - [c225]Meghna Madhusudan, Arvind K. Sharma, Yaguang Li, Jiang Hu, Sachin S. Sapatnekar, Ramesh Hajiani:
Analog Layout Generation using Optimized Primitives. DATE 2021: 1234-1239 - [c224]Vidya A. Chhabria, Yanqing Zhang, Haoxing Ren, Ben Keller, Brucek Khailany, Sachin S. Sapatnekar:
MAVIREC: ML-Aided Vectored IR-Drop Estimation and Classification. DATE 2021: 1825-1828 - [c223]Zamshed I. Chowdhury, Salonik Resch, M. Hüsrev Cilasun, Zhengyang Zhao, Masoud Zabihi, Sachin S. Sapatnekar, Jianping Wang, Ulya R. Karpuzcu:
CAMeleon: Reconfigurable B(T)CAM in Computational RAM. ACM Great Lakes Symposium on VLSI 2021: 57-63 - [c222]Vidya A. Chhabria, Kishor Kunal, Masoud Zabihi, Sachin S. Sapatnekar:
BeGAN: Power Grid Benchmark Generation Using a Process-portable GAN-based Methodology. ICCAD 2021: 1-8 - [c221]Hadi Esmaeilzadeh, Soroush Ghodrati, Jie Gu, Shiyu Guo, Andrew B. Kahng, Joon Kyung Kim, Sean Kinzer, Rohan Mahapatra, Susmita Dey Manasi, Edwin Mascarenhas, Sachin S. Sapatnekar, Ravi Varadarajan, Zhiang Wang, Hanyang Xu, Brahmendra Reddy Yatham, Ziqing Zeng:
VeriGOOD-ML: An Open-Source Flow for Automated ML Hardware Synthesis. ICCAD 2021: 1-7 - [c220]Juzheng Liu, Shiyu Su, Meghna Madhusudan, Mohsen Hassanpourghadi, Samuel Saunders, Qiaochu Zhang, Rezwan A. Rasul, Yaguang Li, Jiang Hu, Arvind Kumar Sharma, Sachin S. Sapatnekar, Ramesh Harjani, Anthony Levi, Sandeep Gupta, Mike Shuo-Wei Chen:
From Specification to Silicon: Towards Analog/Mixed-Signal Design Automation using Surrogate NN Models with Transfer Learning. ICCAD 2021: 1-9 - [c219]Arvind K. Sharma, Meghna Madhusudan, Steven M. Burns, Soner Yaldiz, Parijat Mukherjee, Ramesh Harjani, Sachin S. Sapatnekar:
Performance-Aware Common-Centroid Placement and Routing of Transistor Arrays in Analog Circuits. ICCAD 2021: 1-9 - [c218]Mohammad Abdullah Al Shohel, Vidya A. Chhabria, Nestor E. Evmorfopoulos, Sachin S. Sapatnekar:
Analytical Modeling of Transient Electromigration Stress based on Boundary Reflections. ICCAD 2021: 1-8 - [c217]Tonmoy Dhar, Jitesh Poojary, Ramesh Harjani, Sachin S. Sapatnekar:
Aging of Current DACs and its Impact in Equalizer Circuits. IRPS 2021: 1-6 - [c216]Tonmoy Dhar, Kishor Kunal, Yaguang Li, Yishuang Lin, Meghna Madhusudan, Jitesh Poojary, Arvind K. Sharma, Steven M. Burns, Ramesh Harjani, Jiang Hu, Parijat Mukherjee, Soner Yaldiz, Sachin S. Sapatnekar:
Machine Learning Techniques in Analog Layout Automation. ISPD 2021: 71-72 - [c215]Yaguang Li, Yishuang Lin, Meghna Madhusudan, Arvind K. Sharma, Sachin S. Sapatnekar, Ramesh Harjani, Jiang Hu:
A Circuit Attention Network-Based Actor-Critic Learning Approach to Robust Analog Transistor Sizing. MLCAD 2021: 1-6 - [c214]M. Hüsrev Cilasun, Salonik Resch, Zamshed I. Chowdhury, Masoud Zabihi, Zhengyang Zhao, Thomas Peterson, Jian-Ping Wang, Sachin S. Sapatnekar, Ulya R. Karpuzcu:
Seeds of SEED: H-CRAM: In-memory Homomorphic Search Accelerator using Spintronic Computational RAM. SEED 2021: 70-75 - [i19]Mohammad Abdullah Al Shohel, Vidya A. Chhabria, Sachin S. Sapatnekar:
A New, Computationally Efficient "Blech Criterion" for Immortality in General Interconnects. CoRR abs/2105.08784 (2021) - [i18]Sudipta Mondal, Susmita Dey Manasi, Kishor Kunal, Sachin S. Sapatnekar:
GNNIE: GNN Inference Engine with Load-balancing and Graph-Specific Caching. CoRR abs/2105.10554 (2021) - [i17]Masoud Zabihi, Salonik Resch, M. Hüsrev Cilasun, Zamshed I. Chowdhury, Zhengyang Zhao, Ulya R. Karpuzcu, Jianping Wang, Sachin S. Sapatnekar:
Exploring the Feasibility of Using 3D XPoint as an In-Memory Computing Accelerator. CoRR abs/2106.08402 (2021) - [i16]Vidya A. Chhabria, Sachin S. Sapatnekar:
OpeNPDN: A Neural-network-based Framework for Power Delivery Network Synthesis. CoRR abs/2110.14184 (2021) - [i15]Vidya A. Chhabria, Vipul Ahuja, Ashwath Prabhu, Nikhil Patil, Palkesh Jain, Sachin S. Sapatnekar:
Encoder-Decoder Networks for Analyzing Thermal and Power Delivery Networks. CoRR abs/2110.14197 (2021) - [i14]Salonik Resch, Zamshed I. Chowdhury, M. Hüsrev Cilasun, Masoud Zabihi, Zhengyang Zhao, Jian-Ping Wang, Sachin S. Sapatnekar, Ulya R. Karpuzcu:
Towards Homomorphic Inference Beyond the Edge. CoRR abs/2112.08943 (2021) - [i13]Mohammad Abdullah Al Shohel, Vidya A. Chhabria, Sachin S. Sapatnekar:
A Linear-Time Algorithm for Steady-State Analysis of Electromigration in General Interconnects. CoRR abs/2112.13451 (2021) - 2020
- [j122]Salonik Resch, S. Karen Khatamifard, Zamshed Iqbal Chowdhury, Masoud Zabihi, Zhengyang Zhao, Jianping Wang, Sachin S. Sapatnekar, Ulya R. Karpuzcu:
PIMBALL: Binary Neural Networks in Spintronic Memory. ACM Trans. Archit. Code Optim. 16(4): 41:1-41:26 (2020) - [j121]Qianqian Fan, David J. Lilja, Sachin S. Sapatnekar:
Adaptive-Length Coding of Image Data for Low-Cost Approximate Storage. IEEE Trans. Computers 69(2): 239-252 (2020) - [j120]Susmita Dey Manasi, Farhana Sharmin Snigdha, Sachin S. Sapatnekar:
NeuPart: Using Analytical Models to Drive Energy-Efficient Partitioning of CNN Computations on Cloud-Connected Mobile Clients. IEEE Trans. Very Large Scale Integr. Syst. 28(8): 1844-1857 (2020) - [c213]Vidya A. Chhabria, Andrew B. Kahng, Minsoo Kim, Uday Mallappa, Sachin S. Sapatnekar, Bangqi Xu:
Template-based PDN Synthesis in Floorplan and Placement Using Classifier and CNN Techniques. ASP-DAC 2020: 44-49 - [c212]M. Hüsrev Cilasun, Salonik Resch, Zamshed Iqbal Chowdhury, Erin Olson, Masoud Zabihi, Zhengyang Zhao, Thomas Peterson, Jianping Wang, Sachin S. Sapatnekar, Ulya R. Karpuzcu:
CRAFFT: High Resolution FFT Accelerator In Spintronic Computational RAM. DAC 2020: 1-6 - [c211]Kishor Kunal, Tonmoy Dhar, Meghna Madhusudan, Jitesh Poojary, Arvind K. Sharma, Wenbin Xu, Steven M. Burns, Jiang Hu, Ramesh Harjani, Sachin S. Sapatnekar:
GANA: Graph Convolutional Network Based Automated Netlist Annotation for Analog Circuits. DATE 2020: 55-60 - [c210]Tonmoy Dhar, Kishor Kunal, Yaguang Li, Yishuang Lin, Meghna Madhusudan, Jitesh Poojary, Arvind K. Sharma, Steven M. Burns, Ramesh Harjani, Jiang Hu, Parijat Mukherjee, Soner Yaldiz, Sachin S. Sapatnekar:
The ALIGN Open-Source Analog Layout Generator: v1.0 and Beyond (Invited talk). ICCAD 2020: 54:1-54:2 - [c209]Kishor Kunal, Jitesh Poojary, Tonmoy Dhar, Meghna Madhusudan, Ramesh Harjani, Sachin S. Sapatnekar:
A general approach for identifying hierarchical symmetry constraints for analog circuit layout. ICCAD 2020: 120:1-120:8 - [c208]Yaguang Li, Yishuang Lin, Meghna Madhusudan, Arvind K. Sharma, Wenbin Xu, Sachin S. Sapatnekar, Ramesh Harjani, Jiang Hu:
A Customized Graph Neural Network Model for Guiding Analog IC Placement. ICCAD 2020: 135:1-135:9 - [c207]Kishor Kunal, Tonmoy Dhar, Yaguang Li, Meghna Madhusudan, Jitesh Poojary, Arvind K. Sharma, Wenbin Xu, Steven M. Burns, Ramesh Harjani, Jiang Hu, Parijat Mukherjee, Sachin S. Sapatnekar:
Learning from Experience: Applying ML to Analog Circuit Design. ISPD 2020: 55 - [c206]Tengtao Li, Sachin S. Sapatnekar:
Stress-Induced Performance Shifts in Flexible System-in-Foils Using Ultra-Thin Chips. ISQED 2020: 237-242 - [c205]Yaguang Li, Yishuang Lin, Meghna Madhusudan, Arvind K. Sharma, Wenbin Xu, Sachin S. Sapatnekar, Ramesh Harjani, Jiang Hu:
Exploring a Machine Learning Approach to Performance Driven Analog IC Placement. ISVLSI 2020: 24-29 - [c204]Salonik Resch, S. Karen Khatamifard, Zamshed I. Chowdhury, Masoud Zabihi, Zhengyang Zhao, M. Hüsrev Cilasun, Jianping Wang, Sachin S. Sapatnekar, Ulya R. Karpuzcu:
MOUSE: Inference In Non-volatile Memory for Energy Harvesting Applications. MICRO 2020: 400-414 - [i12]M. Hüsrev Cilasun, Salonik Resch, Zamshed I. Chowdhury, Erin Olson, Masoud Zabihi, Zhengyang Zhao, Thomas Peterson, Keshab K. Parhi, Jianping Wang, Sachin S. Sapatnekar, Ulya R. Karpuzcu:
An Inference and Learning Engine for Spiking Neural Networks in Computational RAM (CRAM). CoRR abs/2006.03007 (2020) - [i11]Tonmoy Dhar, Kishor Kunal, Yaguang Li, Meghna Madhusudan, Jitesh Poojary, Arvind K. Sharma, Wenbin Xu, Steven M. Burns, Ramesh Harjani, Jiang Hu, Desmond A. Kirkpatrick, Parijat Mukherjee, Sachin S. Sapatnekar, Soner Yaldiz:
ALIGN: A System for Automating Analog Layout. CoRR abs/2008.10682 (2020) - [i10]Vidya A. Chhabria, Vipul Ahuja, Ashwath Prabhu, Nikhil Patil, Palkesh Jain, Sachin S. Sapatnekar:
Thermal and IR Drop Analysis Using Convolutional Encoder-Decoder Networks. CoRR abs/2009.09009 (2020) - [i9]Kishor Kunal, Jitesh Poojary, Tonmoy Dhar, Meghna Madhusudan, Ramesh Harjani, Sachin S. Sapatnekar:
A general approach for identifying hierarchical symmetry constraints for analog circuit layout. CoRR abs/2010.00051 (2020) - [i8]Vidya A. Chhabria, Yanqing Zhang, Haoxing Ren, Ben Keller, Brucek Khailany, Sachin S. Sapatnekar:
MAVIREC: ML-Aided Vectored IR-DropEstimation and Classification. CoRR abs/2012.10597 (2020)
2010 – 2019
- 2019
- [j119]Masoud Zabihi, Zamshed Iqbal Chowdhury, Zhengyang Zhao, Ulya R. Karpuzcu, Jianping Wang, Sachin S. Sapatnekar:
In-Memory Processing on the Spintronic CRAM: From Hardware Design to Application Mapping. IEEE Trans. Computers 68(8): 1159-1173 (2019) - [j118]Deepashree Sengupta, Farhana Sharmin Snigdha, Jiang Hu, Sachin S. Sapatnekar:
An Analytical Approach for Error PMF Characterization in Approximate Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(1): 70-83 (2019) - [j117]Farhana Sharmin Snigdha, Deepashree Sengupta, Jiang Hu, Sachin S. Sapatnekar:
Dynamic Approximation of JPEG Hardware. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(2): 295-308 (2019) - [j116]Tengtao Li, Sachin S. Sapatnekar:
Stress-Induced Performance Shifts in 3D DRAMs. ACM Trans. Design Autom. Electr. Syst. 24(5): 51:1-51:21 (2019) - [c203]Farhana Sharmin Snigdha, Ibrahim Ahmed, Susmita Dey Manasi, Meghna G. Mankalale, Jiang Hu, Sachin S. Sapatnekar:
SeFAct: selective feature activation and early classification for CNNs. ASP-DAC 2019: 487-492 - [c202]Tutu Ajayi, Vidya A. Chhabria, Mateus Fogaça, Soheil Hashemi, Abdelrahman Hosny, Andrew B. Kahng, Minsoo Kim, Jeongsup Lee, Uday Mallappa, Marina Neseem, Geraldo Pradipta, Sherief Reda, Mehdi Saligane, Sachin S. Sapatnekar, Carl Sechen, Mohamed Shalan, William Swartz, Lutong Wang, Zhehong Wang, Mingyu Woo, Bangqi Xu:
Toward an Open-Source Digital Flow: First Learnings from the OpenROAD Project. DAC 2019: 76 - [c201]Kishor Kunal, Meghna Madhusudan, Arvind K. Sharma, Wenbin Xu, Steven M. Burns, Ramesh Harjani, Jiang Hu, Desmond A. Kirkpatrick, Sachin S. Sapatnekar:
ALIGN: Open-Source Analog Layout Automation from the Ground Up. DAC 2019: 77 - [c200]