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ORCIDJürgen Teich
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- affiliation: University of Erlangen-Nuremberg
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2020 – today
- 2023
[j122]Alberto Bosio, Mario Barbareschi, Alessandro Savino
, Jie Han, Jürgen Teich:
Special Issue on Approximate Computing: Challenges, Methodologies, Algorithms, and Architectures for Dependable and Secure Systems. IEEE Des. Test 40(3): 5-7 (2023)- [j121]Chetana Pradhan, Martín Letras, Jürgen Teich:
Efficient Table-based Function Approximation on FPGAs Using Interval Splitting and BRAM Instantiation. ACM Trans. Embed. Comput. Syst. 22(4): 73:1-73:24 (2023) - [j120]Jan Spieck, Stefan Wildermann, Jürgen Teich:
A Learning-based Methodology for Scenario-aware Mapping of Soft Real-time Applications onto Heterogeneous MPSoCs. ACM Trans. Design Autom. Electr. Syst. 28(1): 4:1-4:40 (2023) - [j119]Khalil Esper, Stefan Wildermann, Jürgen Teich:
Automatic Synthesis of FSMs for Enforcing Non-functional Requirements on MPSoCs Using Multi-objective Evolutionary Algorithms. ACM Trans. Design Autom. Electr. Syst. 28(6): 98:1-98:20 (2023) - [c479]Tobias Hahn, Daniel Schüll, Stefan Wildermann, Jürgen Teich:
An FPGA Avro Parser Generator for Accelerated Data Stream Processing. BTW 2023: 729-749 - [c478]Jörg Henkel, Lokesh Siddhu, Lars Bauer, Jürgen Teich, Stefan Wildermann, Mehdi B. Tahoori, Mahta Mayahinia, Jerónimo Castrillón, Asif Ali Khan, Hamid Farzaneh, João Paulo C. de Lima, Jian-Jia Chen, Christian Hakert, Kuan-Hsun Chen, Chia-Lin Yang, Hsiang-Yun Cheng:
Special Session - Non-Volatile Memories: Challenges and Opportunities for Embedded System Architectures with Focus on Machine Learning Applications. CASES 2023: 11-20 - [c477]Pierre-Louis Sixdenier, Stefan Wildermann, Martin Ottens, Jürgen Teich:
Seque: Lean and Energy-aware Data Management for IoT Gateways. EDGE 2023: 133-139 - [c476]Muhammad Sabih, Mikail Yayla, Frank Hannig, Jürgen Teich, Jian-Jia Chen:
Robust and Tiny Binary Neural Networks using Gradient-based Explainability Methods. EuroMLSys@EuroSys 2023: 87-93 - [c475]Tobias Hahn, Stefan Wildermann, Jürgen Teich:
SPEAR-JSON: Selective Parsing of JSON to Enable Accelerated Stream Processing on FPGAs. FPL 2023: 189-196 - [c474]Martín Letras, Joachim Falk, Jürgen Teich:
Throughput and Memory Optimization for Parallel Implementations of Dataflow Networks Using Multi-Reader Buffers. NG-RES@HiPEAC 2023: 6:1-6:13 - [c473]Khalil Esper, Jan Spieck, Pierre-Louis Sixdenier, Stefan Wildermann, Jürgen Teich:
RAVEN: Reinforcement Learning for Generating Verifiable Run-Time Requirement Enforcers for MPSoCs. NG-RES@HiPEAC 2023: 7:1-7:16 - [i41]Mark Deutel, Georgios D. Kontes, Christopher Mutschler, Jürgen Teich:
Augmented Random Search for Multi-Objective Bayesian Optimization of Neural Networks. CoRR abs/2305.14109 (2023) - [i40]Patrick Plagwitz, Frank Hannig, Jürgen Teich, Oliver Keszöcze:
To Spike or Not to Spike? A Quantitative Comparison of SNN and CNN FPGA Implementations. CoRR abs/2306.12742 (2023) - 2022
- [j118]Behnaz Pourmohseni, Stefan Wildermann, Fedor Smirnov, Paul E. Meyer, Jürgen Teich:
Task Migration Policy for Thermal-Aware Dynamic Performance Optimization in Many-Core Systems. IEEE Access 10: 33787-33802 (2022) - [j117]Samer Alhaddad, Jens Förstner, Stefan Groth, Daniel Grünewald, Yevgen Grynko, Frank Hannig, Tobias Kenter, Franz-Josef Pfreundt, Christian Plessl, Merlind Schotte, Thomas Steinke, Jürgen Teich, Martin Weiser, Florian Wende:
The HighPerMeshes framework for numerical algorithms on unstructured grids. Concurr. Comput. Pract. Exp. 34(14) (2022) - [j116]Jorge Echavarria, Stefan Wildermann, Oliver Keszöcze, Faramarz Khosravi, Andreas Becher, Jürgen Teich:
Design and error analysis of accuracy-configurable sequential multipliers via segmented carry chains. it Inf. Technol. 64(3): 89-98 (2022) - [j115]Jan Sommer, M. Akif Özkan, Oliver Keszöcze, Jürgen Teich:
Efficient Hardware Acceleration of Sparsely Active Convolutional Spiking Neural Networks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(11): 3767-3778 (2022) - [j114]Jan Spieck, Stefan Wildermann, Jürgen Teich:
On Transferring Application Mapping Knowledge Between Differing MPSoC Architectures. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(11): 4289-4300 (2022) - [j113]Marcel Brand, Frank Hannig, Oliver Keszöcze, Jürgen Teich:
Precision- and Accuracy-Reconfigurable Processor Architectures - An Overview. IEEE Trans. Circuits Syst. II Express Briefs 69(6): 2661-2666 (2022) - [j112]Jens Trautmann, Arthur Beckers, Lennert Wouters, Stefan Wildermann, Ingrid Verbauwhede, Jürgen Teich:
Semi-Automatic Locating of Cryptographic Operations in Side-Channel Traces. IACR Trans. Cryptogr. Hardw. Embed. Syst. 2022(1): 345-366 (2022) - [j111]Franz-Josef Streit, Paul Krüger, Andreas Becher, Stefan Wildermann, Jürgen Teich:
Design and Evaluation of a Tunable PUF Architecture for FPGAs. ACM Trans. Reconfigurable Technol. Syst. 15(1): 7:1-7:27 (2022) - [c472]Jens Trautmann, Nikolaos Patsiatzis, Andreas Becher, Stefan Wildermann, Jürgen Teich:
Putting IMT to the Test: Revisiting and Expanding Interval Matching Techniques and their Calibration for SCA. ASHES@CCS 2022: 65-74 - [c471]Tobias Hahn, Andreas Becher, Stefan Wildermann, Jürgen Teich:
Raw Filtering of JSON Data on FPGAs. DATE 2022: 250-255 - [c470]Muhammad Sabih, Frank Hannig, Jürgen Teich:
DyFiP: explainable AI-based dynamic filter pruning of convolutional neural networks. EuroMLSys@EuroSys 2022: 109-115 - [c469]Jens Trautmann, Jürgen Teich, Stefan Wildermann:
Characterization of Side Channels on FPGA-based Off-The-Shelf Boards against Automated Attacks. FCCM 2022: 1-9 - [c468]Patrick Plagwitz, Frank Hannig, Jürgen Teich:
TRAC: Compilation-Based Design of Transformer Accelerators for FPGAs. FPL 2022: 17-23 - [c467]Jens Trautmann, Nikolaos Patsiatzis, Andreas Becher, Jürgen Teich, Stefan Wildermann:
Real-Time Waveform Matching with a Digitizer at 10 GS/s. FPL 2022: 94-100 - [c466]Jan Sommer, M. Akif Özkan, Oliver Keszöcze, Jürgen Teich:
DSP-Packing: Squeezing Low-precision Arithmetic into FPGA DSP Blocks. FPL 2022: 160-166 - [c465]Tobias Hahn, Stefan Wildermann, Jürgen Teich:
Auto-Tuning of Raw Filters for FPGAs. FPL 2022: 167-175 - [c464]Muhammad Sabih, Ashutosh Mishra, Frank Hannig, Jürgen Teich:
MOSP: Multi-Objective Sensitivity Pruning of Deep Neural Networks. IGSC 2022: 1-8 - [c463]Khalil Esper, Stefan Wildermann, Jürgen Teich:
Multi-Requirement Enforcement of Non-Functional Properties on MPSoCs Using Enforcement FSMs - A Case Study. NG-RES@HiPEAC 2022: 2:1-2:13 - [c462]Peter Brand, Benjamin Hackenberg, Joachim Falk, Jürgen Teich:
Grant Prediction-based Dynamic Power Management for 5G to Reduce Mobile Device Energy Consumption. IWCMC 2022: 647-652 - [c461]Christian Heidorn, Nicolai Meyerhöfer, Christian Schinabeck, Frank Hannig, Jürgen Teich:
Hardware-Aware Evolutionary Filter Pruning. SAMOS 2022: 283-299 - [c460]Pierre-Louis Sixdenier, Stefan Wildermann, Daniel Ziegler, Jürgen Teich:
SIDAM: A Design Space Exploration Framework for Multi-sensor Embedded Systems Powered by Energy Harvesting. SAMOS 2022: 329-345 - [i39]Jan Sommer, M. Akif Özkan, Oliver Keszöcze, Jürgen Teich:
DSP-Packing: Squeezing Low-precision Arithmetic into FPGA DSP Blocks. CoRR abs/2203.11028 (2022) - [i38]Jan Sommer, M. Akif Özkan, Oliver Keszöcze, Jürgen Teich:
Efficient Hardware Acceleration of Sparsely Active Convolutional Spiking Neural Networks. CoRR abs/2203.12437 (2022) - [i37]Chetana Pradhan, Martín Letras, Jürgen Teich:
Efficient Table-based Function Approximation on FPGAs using Interval Splitting and BRAM Instantiation. CoRR abs/2204.02443 (2022) - [i36]Tobias Hahn, Andreas Becher, Stefan Wildermann, Jürgen Teich:
Raw Filtering of JSON Data on FPGAs. CoRR abs/2205.05464 (2022) - [i35]Mark Deutel, Philipp Woller, Christopher Mutschler, Jürgen Teich:
Deployment of Energy-Efficient Deep Learning Models on Cortex-M based Microcontrollers using Deep Compression. CoRR abs/2205.10369 (2022) - [i34]Jens Trautmann, Nikolaos Patsiatzis, Andreas Becher, Jürgen Teich, Stefan Wildermann:
Real-Time Waveform Matching with a Digitizer at 10 GS/s. CoRR abs/2206.10368 (2022) - 2021
- [j110]Frank Hannig, Jürgen Teich:
Open Source Hardware. Computer 54(10): 111-115 (2021) - [j109]Marcel Brand, Michael Witterauf, Éricles Sousa, Alexandru Tanase, Frank Hannig, Jürgen Teich:
*-Predictable MPSoC execution of real-time control applications using invasive computing. Concurr. Comput. Pract. Exp. 33(14) (2021) - [j108]Lekshmi Beena Gopalakrishnan Nair, Andreas Becher, Stefan Wildermann, Klaus Meyer-Wegener, Jürgen Teich:
Speculative Dynamic Reconfiguration and Table Prefetching Using Query Look-Ahead in the ReProVide Near-Data-Processing System. Datenbank-Spektrum 21(1): 55-64 (2021) - [j107]M. Akif Özkan, Burak Ok, Bo Qiao, Jürgen Teich, Frank Hannig:
HipaccVX: wedding of OpenVX and DSL-based code generation. J. Real Time Image Process. 18(3): 765-777 (2021) - [j106]Michael Witterauf, Dominik Walter, Frank Hannig, Jürgen Teich:
Symbolic Loop Compilation for Tightly Coupled Processor Arrays. ACM Trans. Embed. Comput. Syst. 20(5): 49:1-49:31 (2021) - [j105]Faramarz Khosravi, Alexander Raß, Jürgen Teich:
Efficient Computation of Probabilistic Dominance in Multi-objective Optimization. ACM Trans. Evol. Learn. Optim. 1(4): 15:1-15:26 (2021) - [j104]Peter Brand, Joachim Falk, Jonathan Ah Sue, Johannes Brendel, Ralph Hasholzner, Jürgen Teich:
Adaptive Predictive Power Management for Mobile LTE Devices. IEEE Trans. Mob. Comput. 20(8): 2518-2535 (2021) - [j103]Martín Letras, Joachim Falk, Tobias Schwarzer, Jürgen Teich:
Multi-objective Optimization of Mapping Dataflow Applications to MPSoCs Using a Hybrid Evaluation Combining Analytic Models and Measurements. ACM Trans. Design Autom. Electr. Syst. 26(3): 18:1-18:33 (2021) - [c459]Franz-Josef Streit, Stefan Wildermann, Michael Pschyklenk, Jürgen Teich:
Providing Tamper-Secure SoC Updates Through Reconfigurable Hardware. ARC 2021: 242-253 - [c458]Jürgen Teich, Pouya Mahmoody, Behnaz Pourmohseni, Sascha Roloff, Wolfgang Schröder-Preikschat, Stefan Wildermann:
Run-Time Enforcement of Non-functional Program Properties on MPSoCs. A Journey of Embedded and Cyber-Physical Systems 2021: 125-149 - [c457]Jorge Echavarria, Stefan Wildermann, Jürgen Teich:
Approximate Logic Synthesis of Very Large Boolean Networks. DATE 2021: 1552-1557 - [c456]Muhammad Sabih, Frank Hannig, Jürgen Teich:
Fault-Tolerant Low-Precision DNNs using Explainable AI. DSN Workshops 2021: 166-174 - [c455]Alberto Bosio, Ian O'Connor, Marcello Traiola, Jorge Echavarria, Jürgen Teich, Muhammad Abdullah Hanif, Muhammad Shafique, Said Hamdioui, Bastien Deveautour, Patrick Girard, Arnaud Virazel, Koen Bertels:
Emerging Computing Devices: Challenges and Opportunities for Test and Reliability*. ETS 2021: 1-10 - [c454]Patrick Plagwitz, Frank Hannig, Martin Ströbel, Christoph Strohmeyer, Jürgen Teich:
A Safari through FPGA-based Neural Network Compilation and Design Automation Flows. FCCM 2021: 10-19 - [c453]Franz-Josef Streit, Paul Krüger, Andreas Becher, Jens Schlumberger, Stefan Wildermann, Jürgen Teich:
Choice - A Tunable PUF-Design for FPGAs. FPL 2021: 38-44 - [c452]Christian Heidorn, Dominik Walter, Yunus Emre Candir, Frank Hannig, Jürgen Teich:
Hand Sign Recognition via Deep Learning on Tightly Coupled Processor Arrays. FPL 2021: 388 - [c451]Khalil Esper, Stefan Wildermann, Jürgen Teich:
A Comparative Evaluation of Latency-Aware Energy Optimization Approaches in Many-Core Systems (Invited Paper). NG-RES@HiPEAC 2021: 1:1-1:12 - [c450]Marcello Traiola, Jorge Echavarria, Alberto Bosio, Jürgen Teich, Ian O'Connor:
Design Space Exploration of Approximation-Based Quadruple Modular Redundancy Circuits. ICCAD 2021: 1-9 - [c449]Bo Qiao, Jürgen Teich, Frank Hannig:
An Efficient Approach for Image Border Handling on GPUs via Iteration Space Partitioning. IPDPS Workshops 2021: 387-396 - [c448]Peter Brand, Joachim Falk, Eduard Potwigin, Jürgen Teich:
Multi-Step Ahead Grant Prediction for Dynamic Power Management in Cellular Modems. ISNCC 2021: 1-6 - [c447]Khalil Esper, Stefan Wildermann, Jürgen Teich:
Enforcement FSMs: specification and verification of non-functional properties of program executions on MPSoCs. MEMOCODE 2021: 21-31 - [c446]Dominik Walter, Jürgen Teich:
LION: real-time I/O transfer control for massively parallel processor arrays. MEMOCODE 2021: 32-43 - [c445]Jan Spieck, Stefan Wildermann, Jürgen Teich:
Domain-Adaptive Soft Real-Time Hybrid Application Mapping for MPSoCs. MLCAD 2021: 1-6 - [c444]Jens Schlumberger, Stefan Wildermann, Jürgen Teich:
CORSICA: A Framework for Conducting Real-World Side-Channel Analysis. NTMS 2021: 1-5 - [c443]Armin Schuster, Christian Heidorn, Marcel Brand, Oliver Keszöcze, Jürgen Teich:
Design Space Exploration of Time, Energy, and Error Rate Trade-offs for CNNs Using Accuracy-Programmable Instruction Set Processors. PKDD/ECML Workshops (1) 2021: 375-389 - [c442]Oliver Keszöcze, Marcel Brand, Michael Witterauf, Christian Heidorn, Jürgen Teich:
Aarith: an arbitrary precision number library. SAC 2021: 529-534 - [c441]Stefan Groth, Jürgen Teich, Frank Hannig:
Efficient Application of Tensor Core Units for Convolving Images. SCOPES 2021: 1-6 - [i33]Michael Witterauf, Dominik Walter, Frank Hannig, Jürgen Teich:
Symbolic Loop Compilation for Tightly Coupled Processor Arrays. CoRR abs/2101.04395 (2021) - [i32]Jorge Echavarria, Stefan Wildermann, Oliver Keszöcze, Faramarz Khosravi, Andreas Becher, Jürgen Teich:
On the Approximation of Accuracy-configurable Sequential Multipliers via Segmented Carry Chains. CoRR abs/2105.05588 (2021) - 2020
- [j102]Sandra Mattauch, Katja Lohmann, Frank Hannig, Daniel Lohmann, Jürgen Teich:
A bibliometric approach for detecting the gender gap in computer science. Commun. ACM 63(5): 74-80 (2020) - [j101]M. Akif Özkan, Arsène Pérard-Gayot, Richard Membarth, Philipp Slusallek, Roland Leißa, Sebastian Hack, Jürgen Teich, Frank Hannig:
AnyHLS: High-Level Synthesis With Partial Evaluation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(11): 3202-3214 (2020) - [c440]Bo Wang, Aneek Imtiaz, Joachim Falk, Michael Glaß, Jürgen Teich:
Exploration of Power Domain Partitioning with Concurrent Task Mapping and Scheduling for Application-Specific Multi-core SoCs. ARCS 2020: 153-167 - [c439]Marcel Brand, Michael Witterauf, Alberto Bosio, Jürgen Teich:
Anytime Floating-Point Addition and Multiplication-Concepts and Implementations. ASAP 2020: 157-164 - [c438]Jürgen Teich, Behnaz Pourmohseni, Oliver Keszöcze, Jan Spieck, Stefan Wildermann:
Run-Time Enforcement of Non-Functional Application Requirements in Heterogeneous Many-Core Systems. ASP-DAC 2020: 629-636 - [c437]Stefan Groth, Daniel Grünewald, Jürgen Teich, Frank Hannig:
A runtime system for finite element methods in a partitioned global address space. CF 2020: 39-48 - [c436]Jorge Echavarria, Stefan Wildermann, Oliver Keszöcze, Jürgen Teich:
Probabilistic Error Propagation through Approximated Boolean Networks. DAC 2020: 1-6 - [c435]Bo Qiao, M. Akif Özkan, Jürgen Teich, Frank Hannig:
The Best of Both Worlds: Combining CUDA Graph with an Image Processing DSL. DAC 2020: 1-6 - [c434]Jan Spieck, Stefan Wildermann, Jürgen Teich:
Scenario-Based Soft Real-Time Hybrid Application Mapping for MPSoCs. DAC 2020: 1-6 - [c433]Fedor Smirnov, Behnaz Pourmohseni, Jürgen Teich:
Using Learning Classifier Systems for the DSE of Adaptive Embedded Systems. DATE 2020: 957-962 - [c432]Lekshmi B. G., Andreas Becher, Klaus Meyer-Wegener, Stefan Wildermann, Jürgen Teich:
SQL Query Processing Using an Integrated FPGA-based Near-Data Accelerator in ReProVide. EDBT 2020: 639-642 - [c431]Samer Alhaddad, Jens Förstner, Stefan Groth, Daniel Grünewald, Yevgen Grynko, Frank Hannig, Tobias Kenter, Franz-Josef Pfreundt, Christian Plessl, Merlind Schotte, Thomas Steinke, Jürgen Teich, Martin Weiser, Florian Wende:
HighPerMeshes - A Domain-Specific Language for Numerical Algorithms on Unstructured Grids. Euro-Par Workshops 2020: 185-196 - [c430]Bertrand Simon, Joachim Falk, Nicole Megow, Jürgen Teich:
Energy Minimization in DAG Scheduling on MPSoCs at Run-Time: Theory and Practice. NG-RES@HiPEAC 2020: 2:1-2:13 - [c429]Behnaz Pourmohseni, Fedor Smirnov, Stefan Wildermann, Jürgen Teich:
Real-Time Task Migration for Dynamic Resource Management in Many-Core Systems. NG-RES@HiPEAC 2020: 5:1-5:14 - [c428]Franz-Josef Streit, Florian Fritz, Andreas Becher, Stefan Wildermann, Stefan Werner, Martin Schmidt-Korth, Michael Pschyklenk, Jürgen Teich:
Secure Boot from Non-Volatile Memory for Programmable SoC Architectures. HOST 2020: 102-110 - [c427]Dominik Walter, Michael Witterauf, Jürgen Teich:
Real-time Scheduling of I/O Transfers for Massively Parallel Processor Arrays. MEMOCODE 2020: 1-11 - [c426]Bo Qiao, Oliver Reiche, Jürgen Teich, Frank Hannig:
Unveiling kernel concurrency in multiresolution filters on GPUs with an image processing DSL. GPGPU@PPoPP 2020: 11-20 - [c425]Christian Heidorn, Frank Hannig, Jürgen Teich:
Design space exploration for layer-parallel execution of convolutional neural networks on CGRAs. SCOPES 2020: 26-31 - [c424]Bo Qiao, Oliver Reiche, M. Akif Özkan, Jürgen Teich, Frank Hannig:
Efficient parallel reduction on GPUs with Hipacc. SCOPES 2020: 58-61 - [c423]Arvind Thumatti K. R., Marcel Brand, Christian Heidorn, Srinivas Boppu, Frank Hannig, Jürgen Teich:
Hardware Implementation of Hyperbolic Tangent Activation Function for Floating Point Formats. VDAT 2020: 1-6 - [c422]Peter Brand, Muhammad Sabih, Joachim Falk, Jonathan Ah Sue, Jürgen Teich:
Clustering-Based Scenario-Aware LTE Grant Prediction. WCNC 2020: 1-7 - [p17]Christian Lengauer, Sven Apel, Matthias Bolten, Shigeru Chiba, Ulrich Rüde, Jürgen Teich, Armin Größlinger, Frank Hannig, Harald Köstler, Lisa Claus, Alexander Grebhahn, Stefan Groth, Stefan Kronawitter, Sebastian Kuckuk, Hannah Rittich, Christian Schmitt, Jonas Schmitt:
ExaStencils: Advanced Multigrid Solver Generation. Software for Exascale Computing 2020: 405-452 - [i31]M. Akif Özkan, Arsène Pérard-Gayot, Richard Membarth, Philipp Slusallek, Roland Leißa, Sebastian Hack, Jürgen Teich, Frank Hannig:
AnyHLS: High-Level Synthesis with Partial Evaluation. CoRR abs/2002.05796 (2020) - [i30]Franz-Josef Streit, Florian Fritz, Andreas Becher, Stefan Wildermann, Stefan Werner, Martin Schmidt-Korth, Michael Pschyklenk, Jürgen Teich:
Secure Boot from Non-Volatile Memory for Programmable SoC Architectures. CoRR abs/2004.09453 (2020) - [i29]Muhammad Sabih, Frank Hannig, Jürgen Teich:
Utilizing Explainable AI for Quantization and Pruning of Deep Neural Networks. CoRR abs/2008.09072 (2020) - [i28]M. Akif Özkan, Burak Ok, Bo Qiao, Jürgen Teich, Frank Hannig:
HipaccVX: Wedding of OpenVX and DSL-based Code Generation. CoRR abs/2008.11476 (2020)
2010 – 2019
- 2019
- [b8]Sascha Roloff, Frank Hannig, Jürgen Teich:
Modeling and Simulation of Invasive Applications and Architectures. Computer Architecture and Design Methodologies, Springer 2019, ISBN 978-981-13-8386-1, pp. i-xv, 1-168 - [j100]Jürgen Teich, Franco Fummi:
Conference Reports: Recap of DATE 2019 in Florence, Italy. IEEE Des. Test 36(4): 59-61 (2019) - [j99]Christian Heidorn, Michael Witterauf, Frank Hannig, Jürgen Teich:
Efficient Mapping of CNNs onto Tightly Coupled Processor Arrays. J. Comput. 14(8): 541-556 (2019) - [j98]Behnaz Pourmohseni, Stefan Wildermann, Michael Glaß, Jürgen Teich:
Hard real-time application mapping reconfiguration for NoC-based many-core systems. Real Time Syst. 55(2): 433-469 (2019) - [j97]Fedor Smirnov, Behnaz Pourmohseni, Michael Glaß, Jürgen Teich:
IGOR, Get Me the Optimum! Prioritizing Important Design Decisions During the DSE of Embedded Systems. ACM Trans. Embed. Comput. Syst. 18(5s): 78:1-78:22 (2019) - [j96]Richard Membarth, Hritam Dutta, Frank Hannig, Jürgen Teich:
Efficient Mapping of Streaming Applications for Image Processing on Graphics Cards. Trans. High Perform. Embed. Archit. Compil. 5: 1-20 (2019) - [j95]Fedor Smirnov, Felix Reimann, Jürgen Teich, Michael Glaß:
Automatic Optimization of the VLAN Partitioning in Automotive Communication Networks. ACM Trans. Design Autom. Electr. Syst. 24(1): 9:1-9:23 (2019) - [j94]Tobias Schwarzer, Joachim Falk, Simone Müller, Martín Letras, Christian Heidorn, Stefan Wildermann, Jürgen Teich:
Compilation of Dataflow Applications for Multi-Cores using Adaptive Multi-Objective Optimization. ACM Trans. Design Autom. Electr. Syst. 24(3): 29:1-29:23 (2019) - [c421]Jörg Fickenscher, Frank Hannig, Jürgen Teich:
DSL-Based Acceleration of Automotive Environment Perception and Mapping Algorithms for Embedded CPUs, GPUs, and FPGAs. ARCS 2019: 71-86 - [c420]Andreas Becher, Achim Herrmann, Stefan Wildermann, Jürgen Teich:
ReProVide: Towards Utilizing Heterogeneous Partially Reconfigurable Architectures for Near-Memory Data Processing. BTW (Workshops) 2019: 51-70 - [c419]Marcel Brand, Michael Witterauf, Frank Hannig, Jürgen Teich:
Anytime instructions for programmable accuracy floating-point arithmetic. CF 2019: 215-219 - [c418]Bo Qiao, Oliver Reiche, Frank Hannig, Jürgen Teich:
From Loop Fusion to Kernel Fusion: A Domain-Specific Approach to Locality Optimization. CGO 2019: 242-253 - [c417]Andreas Becher, Jürgen Teich:
In situ Statistics Generation within partially reconfigurable Hardware Accelerators for Query Processing. DaMoN 2019: 20:1-20:3 - [c416]Hananeh Aliee, Faramarz Khosravi, Jürgen Teich:
Efficient Treatment of Uncertainty in System Reliability Analysis using Importance Measures. DSN 2019: 76-87 - [c415]Behnaz Pourmohseni, Fedor Smirnov, Stefan Wildermann, Jürgen Teich:
Isolation-Aware Timing Analysis and Design Space Exploration for Predictable and Composable Many-Core Systems. ECRTS 2019: 12:1-12:24 - [c414]