BibTeX record conf/apccas/LeiZHW18

download as .bib file

@inproceedings{DBLP:conf/apccas/LeiZHW18,
  author       = {Yu Lei and
                  Chenchang Zhan and
                  Chenyu Huang and
                  Lidan Wang},
  title        = {A Chip-Area-Efficient Subthreshold {CMOS} Voltage Reference with High
                  {PSRR} Based on Compensated {\(\Delta\)}VGS of {NMOS} Transistors},
  booktitle    = {2018 {IEEE} Asia Pacific Conference on Circuits and Systems, {APCCAS}
                  2018, Chengdu, China, October 26-30, 2018},
  pages        = {497--500},
  publisher    = {{IEEE}},
  year         = {2018},
  url          = {https://doi.org/10.1109/APCCAS.2018.8605633},
  doi          = {10.1109/APCCAS.2018.8605633},
  timestamp    = {Wed, 16 Oct 2019 14:14:50 +0200},
  biburl       = {https://dblp.org/rec/conf/apccas/LeiZHW18.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
a service of  Schloss Dagstuhl - Leibniz Center for Informatics

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.