BibTeX record conf/asicon/WangWYYHZ15

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@inproceedings{DBLP:conf/asicon/WangWYYHZ15,
  author       = {Jielin Wang and
                  Weizhen Wang and
                  Jianwei Yang and
                  Zhiyi Yu and
                  Jun Han and
                  Xiaoyang Zeng},
  title        = {Parallel implementation of {AES} on 2.5D multicore platform with hardware
                  and software co-design},
  booktitle    = {2015 {IEEE} 11th International Conference on ASIC, {ASICON} 2015,
                  Chengdu, China, November 3-6, 2015},
  pages        = {1--4},
  publisher    = {{IEEE}},
  year         = {2015},
  url          = {https://doi.org/10.1109/ASICON.2015.7517001},
  doi          = {10.1109/ASICON.2015.7517001},
  timestamp    = {Wed, 16 Oct 2019 14:14:56 +0200},
  biburl       = {https://dblp.org/rec/conf/asicon/WangWYYHZ15.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
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