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BibTeX record conf/aspdac/ChandarV01
@inproceedings{DBLP:conf/aspdac/ChandarV01, author = {Subash Chandar G. and S. Vaideeswaran}, editor = {Satoshi Goto}, title = {Addressing verification bottlenecks of fully synthesized processor cores using equivalence checkers}, booktitle = {Proceedings of {ASP-DAC} 2001, Asia and South Pacific Design Automation Conference 2001, January 30-February 2, 2001, Yokohama, Japan}, pages = {175--180}, publisher = {{ACM}}, year = {2001}, url = {https://doi.org/10.1145/370155.370316}, doi = {10.1145/370155.370316}, timestamp = {Mon, 06 Apr 2020 17:04:28 +0200}, biburl = {https://dblp.org/rec/conf/aspdac/ChandarV01.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
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