BibTeX record conf/aspdac/GuYLW17

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@inproceedings{DBLP:conf/aspdac/GuYLW17,
  author       = {Jiangyuan Gu and
                  Shouyi Yin and
                  Leibo Liu and
                  Shaojun Wei},
  title        = {Energy-aware loops mapping on multi-vdd CGRAs without performance
                  degradation},
  booktitle    = {22nd Asia and South Pacific Design Automation Conference, {ASP-DAC}
                  2017, Chiba, Japan, January 16-19, 2017},
  pages        = {312--317},
  publisher    = {{IEEE}},
  year         = {2017},
  url          = {https://doi.org/10.1109/ASPDAC.2017.7858341},
  doi          = {10.1109/ASPDAC.2017.7858341},
  timestamp    = {Fri, 27 Mar 2020 09:02:54 +0100},
  biburl       = {https://dblp.org/rec/conf/aspdac/GuYLW17.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
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