BibTeX record conf/aspdac/HashimotoO01

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@inproceedings{DBLP:conf/aspdac/HashimotoO01,
  author       = {Masanori Hashimoto and
                  Hidetoshi Onodera},
  editor       = {Satoshi Goto},
  title        = {Post-layout transistor sizing for power reduction in cell-based design},
  booktitle    = {Proceedings of {ASP-DAC} 2001, Asia and South Pacific Design Automation
                  Conference 2001, January 30-February 2, 2001, Yokohama, Japan},
  pages        = {359--365},
  publisher    = {{ACM}},
  year         = {2001},
  url          = {https://doi.org/10.1145/370155.370392},
  doi          = {10.1145/370155.370392},
  timestamp    = {Wed, 16 Oct 2019 14:14:52 +0200},
  biburl       = {https://dblp.org/rec/conf/aspdac/HashimotoO01.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
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