BibTeX record conf/asscc/LuZP16

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@inproceedings{DBLP:conf/asscc/LuZP16,
  author    = {Shengshuo Lu and
               Zhengya Zhang and
               Marios C. Papaefthymiou},
  title     = {A 5.5GHz 0.84TOPS/mm\({}^{\mbox{2}}\) neural network engine with stream
               architecture and resonant clock mesh},
  booktitle = {{IEEE} Asian Solid-State Circuits Conference, {A-SSCC} 2016, Toyama,
               Japan, November 7-9, 2016},
  pages     = {133--136},
  year      = {2016},
  crossref  = {DBLP:conf/asscc/2016},
  url       = {https://doi.org/10.1109/ASSCC.2016.7844153},
  doi       = {10.1109/ASSCC.2016.7844153},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/asscc/LuZP16},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/asscc/2016,
  title     = {{IEEE} Asian Solid-State Circuits Conference, {A-SSCC} 2016, Toyama,
               Japan, November 7-9, 2016},
  publisher = {{IEEE}},
  year      = {2016},
  url       = {https://ieeexplore.ieee.org/xpl/conhome/7833314/proceeding},
  isbn      = {978-1-5090-3699-8},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/asscc/2016},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
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