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BibTeX record conf/cicc/NakamuraDT18
@inproceedings{DBLP:conf/cicc/NakamuraDT18, author = {Toshiki Nakamura and Yoshiaki Deguchi and Ken Takeuchi}, title = {9.1x Error acceptable adaptive artificial neural network coupled {LDPC} {ECC} for charge-trap and floating-gate 3D-NAND flash memories}, booktitle = {2018 {IEEE} Custom Integrated Circuits Conference, {CICC} 2018, San Diego, CA, USA, April 8-11, 2018}, pages = {1--4}, publisher = {{IEEE}}, year = {2018}, url = {https://doi.org/10.1109/CICC.2018.8357064}, doi = {10.1109/CICC.2018.8357064}, timestamp = {Wed, 16 Oct 2019 14:14:52 +0200}, biburl = {https://dblp.org/rec/conf/cicc/NakamuraDT18.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
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