BibTeX record conf/date/ChenJLLGL17

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@inproceedings{DBLP:conf/date/ChenJLLGL17,
  author       = {Di Chen and
                  Hai Jin and
                  Xiaofei Liao and
                  Haikun Liu and
                  Rentong Guo and
                  Dong Liu},
  editor       = {David Atienza and
                  Giorgio Di Natale},
  title        = {{MALRU:} Miss-penalty aware LRU-based cache replacement for hybrid
                  memory systems},
  booktitle    = {Design, Automation {\&} Test in Europe Conference {\&} Exhibition,
                  {DATE} 2017, Lausanne, Switzerland, March 27-31, 2017},
  pages        = {1086--1091},
  publisher    = {{IEEE}},
  year         = {2017},
  url          = {https://doi.org/10.23919/DATE.2017.7927151},
  doi          = {10.23919/DATE.2017.7927151},
  timestamp    = {Wed, 16 Oct 2019 14:14:53 +0200},
  biburl       = {https://dblp.org/rec/conf/date/ChenJLLGL17.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
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