BibTeX record conf/esscirc/BaeJPCKJ14

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@inproceedings{DBLP:conf/esscirc/BaeJPCKJ14,
  author       = {Woo{-}Rham Bae and
                  Gyu{-}Seob Jeong and
                  Kwanseo Park and
                  Sung{-}Yong Cho and
                  Yoonsoo Kim and
                  Deog{-}Kyoon Jeong},
  title        = {A 0.36 pJ/bit, 12.5 Gb/s forwarded-clock receiver with a sample swapping
                  scheme and a half-bit delay line},
  booktitle    = {{ESSCIRC} 2014 - 40th European Solid State Circuits Conference, Venice
                  Lido, Italy, September 22-26, 2014},
  pages        = {447--450},
  publisher    = {{IEEE}},
  year         = {2014},
  url          = {https://doi.org/10.1109/ESSCIRC.2014.6942118},
  doi          = {10.1109/ESSCIRC.2014.6942118},
  timestamp    = {Wed, 16 Oct 2019 14:14:53 +0200},
  biburl       = {https://dblp.org/rec/conf/esscirc/BaeJPCKJ14.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}