BibTeX record conf/iccad/PuiCMYY17

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@inproceedings{DBLP:conf/iccad/PuiCMYY17,
  author       = {Chak{-}Wa Pui and
                  Gengjie Chen and
                  Yuzhe Ma and
                  Evangeline F. Y. Young and
                  Bei Yu},
  editor       = {Sri Parameswaran},
  title        = {Clock-aware ultrascale {FPGA} placement with machine learning routability
                  prediction: (Invited paper)},
  booktitle    = {2017 {IEEE/ACM} International Conference on Computer-Aided Design,
                  {ICCAD} 2017, Irvine, CA, USA, November 13-16, 2017},
  pages        = {929--936},
  publisher    = {{IEEE}},
  year         = {2017},
  url          = {https://doi.org/10.1109/ICCAD.2017.8203880},
  doi          = {10.1109/ICCAD.2017.8203880},
  timestamp    = {Wed, 16 Oct 2019 14:14:49 +0200},
  biburl       = {https://dblp.org/rec/conf/iccad/PuiCMYY17.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
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