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BibTeX record conf/iscas/YanamanamandaLW05
@inproceedings{DBLP:conf/iscas/YanamanamandaLW05, author = {Satish K. Yanamanamanda and Jun Li and Janet Meiling Wang}, title = {Uncertainty modeling of gate delay considering multiple input switching}, booktitle = {International Symposium on Circuits and Systems {(ISCAS} 2005), 23-26 May 2005, Kobe, Japan}, pages = {2457--2460}, publisher = {{IEEE}}, year = {2005}, url = {https://doi.org/10.1109/ISCAS.2005.1465123}, doi = {10.1109/ISCAS.2005.1465123}, timestamp = {Thu, 24 Sep 2020 15:35:02 +0200}, biburl = {https://dblp.org/rec/conf/iscas/YanamanamandaLW05.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
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