BibTeX record conf/isqed/AsharSV17

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@inproceedings{DBLP:conf/isqed/AsharSV17,
  author       = {Pranav Ashar and
                  Vikas Sachdeva and
                  Vinod Viswanath},
  title        = {Failures and verification solutions related to untimed paths in SOCs},
  booktitle    = {18th International Symposium on Quality Electronic Design, {ISQED}
                  2017, Santa Clara, CA, USA, March 14-15, 2017},
  pages        = {460--465},
  publisher    = {{IEEE}},
  year         = {2017},
  url          = {https://doi.org/10.1109/ISQED.2017.7918359},
  doi          = {10.1109/ISQED.2017.7918359},
  timestamp    = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl       = {https://dblp.org/rec/conf/isqed/AsharSV17.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
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