BibTeX record conf/isscc/KulkarniTANATD15

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@inproceedings{DBLP:conf/isscc/KulkarniTANATD15,
  author    = {Jaydeep P. Kulkarni and
               Carlos Tokunaga and
               Paolo A. Aseron and
               Trang Nguyen and
               Charles Augustine and
               James Tschanz and
               Vivek De},
  title     = {4.7 {A} 409GOPS/W adaptive and resilient domino register file in 22nm
               tri-gate {CMOS} featuring in-situ timing margin and error detection
               for tolerance to within-die variation, voltage droop, temperature
               and aging},
  booktitle = {2015 {IEEE} International Solid-State Circuits Conference, {ISSCC}
               2015, Digest of Technical Papers, San Francisco, CA, USA, February
               22-26, 2015},
  pages     = {1--3},
  year      = {2015},
  crossref  = {DBLP:conf/isscc/2015},
  url       = {https://doi.org/10.1109/ISSCC.2015.7062936},
  doi       = {10.1109/ISSCC.2015.7062936},
  timestamp = {Wed, 17 May 2017 14:25:07 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/isscc/KulkarniTANATD15},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/isscc/2015,
  title     = {2015 {IEEE} International Solid-State Circuits Conference, {ISSCC}
               2015, Digest of Technical Papers, San Francisco, CA, USA, February
               22-26, 2015},
  publisher = {{IEEE}},
  year      = {2015},
  url       = {http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=7054075},
  isbn      = {978-1-4799-6223-5},
  timestamp = {Tue, 24 Mar 2015 08:51:19 +0100},
  biburl    = {https://dblp.org/rec/bib/conf/isscc/2015},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
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