BibTeX record conf/isscc/YamaokaMSO08

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@inproceedings{DBLP:conf/isscc/YamaokaMSO08,
  author       = {Masanao Yamaoka and
                  Noriaki Maeda and
                  Yasuhisa Shimazaki and
                  Kenichi Osada},
  title        = {65nm Low-Power High-Density {SRAM} Operable at 1.0V under 3{\(\sigma\)}
                  Systematic Variation Using Separate Vth Monitoring and Body Bias for
                  {NMOS} and {PMOS}},
  booktitle    = {2008 {IEEE} International Solid-State Circuits Conference, {ISSCC}
                  2008, Digest of Technical Papers, San Francisco, CA, USA, February
                  3-7, 2008},
  pages        = {384--385},
  publisher    = {{IEEE}},
  year         = {2008},
  url          = {https://doi.org/10.1109/ISSCC.2008.4523218},
  doi          = {10.1109/ISSCC.2008.4523218},
  timestamp    = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl       = {https://dblp.org/rec/conf/isscc/YamaokaMSO08.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}