BibTeX record conf/isvlsi/VeredasSZP06

download as .bib file

@inproceedings{DBLP:conf/isvlsi/VeredasSZP06,
  author       = {Francisco{-}Javier Veredas and
                  Michael Scheppler and
                  Bumei Zhai and
                  Hans{-}J{\"{o}}rg Pfleiderer},
  title        = {Regular Routing Architecture for a LUT-based {MPGA}},
  booktitle    = {2006 {IEEE} Computer Society Annual Symposium on {VLSI} {(ISVLSI}
                  2006), 2-3 March 2006, Karlsruhe, Germany},
  pages        = {257--262},
  publisher    = {{IEEE} Computer Society},
  year         = {2006},
  url          = {https://doi.org/10.1109/ISVLSI.2006.78},
  doi          = {10.1109/ISVLSI.2006.78},
  timestamp    = {Fri, 24 Mar 2023 00:02:41 +0100},
  biburl       = {https://dblp.org/rec/conf/isvlsi/VeredasSZP06.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
a service of  Schloss Dagstuhl - Leibniz Center for Informatics

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.