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BibTeX record conf/mse/ClarkVHDW17
@inproceedings{DBLP:conf/mse/ClarkVHDW17, author = {Lawrence T. Clark and Vinay Vashishtha and David M. Harris and Samuel Dietrich and Zunyan Wang}, title = {Design flows and collateral for the {ASAP7} 7nm FinFET predictive process design kit}, booktitle = {2017 {IEEE} International Conference on Microelectronic Systems Education, {MSE} 2017, Lake Louise, AB, Canada, May 11-12, 2017}, pages = {1--4}, publisher = {{IEEE}}, year = {2017}, url = {https://doi.org/10.1109/MSE.2017.7945071}, doi = {10.1109/MSE.2017.7945071}, timestamp = {Wed, 16 Oct 2019 14:14:53 +0200}, biburl = {https://dblp.org/rec/conf/mse/ClarkVHDW17.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
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