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BibTeX record conf/patmos/MinanaGHLC05
@inproceedings{DBLP:conf/patmos/MinanaGHLC05, author = {Guadalupe Mi{\~{n}}ana and Oscar Garnica and Jos{\'{e}} Ignacio Hidalgo and Juan Lanchares and Jos{\'{e}} Manuel Colmenar}, editor = {Vassilis Paliouras and Johan Vounckx and Diederik Verkest}, title = {Power Reduction of Superscalar Processor Functional Units by Resizing Adder-Width}, booktitle = {Integrated Circuit and System Design, Power and Timing Modeling, Optimization and Simulation, 15th International Workshop, {PATMOS} 2005, Leuven, Belgium, September 21-23, 2005, Proceedings}, series = {Lecture Notes in Computer Science}, volume = {3728}, pages = {40--48}, publisher = {Springer}, year = {2005}, url = {https://doi.org/10.1007/11556930\_5}, doi = {10.1007/11556930\_5}, timestamp = {Sat, 09 Apr 2022 12:43:17 +0200}, biburl = {https://dblp.org/rec/conf/patmos/MinanaGHLC05.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
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