BibTeX record conf/patmos/VeredasC05

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@inproceedings{DBLP:conf/patmos/VeredasC05,
  author       = {Francisco{-}Javier Veredas and
                  Jordi Carrabina},
  editor       = {Vassilis Paliouras and
                  Johan Vounckx and
                  Diederik Verkest},
  title        = {Power Dissipation Impact of the Technology Mapping Synthesis on Look-Up
                  Table Architectures},
  booktitle    = {Integrated Circuit and System Design, Power and Timing Modeling, Optimization
                  and Simulation, 15th International Workshop, {PATMOS} 2005, Leuven,
                  Belgium, September 21-23, 2005, Proceedings},
  series       = {Lecture Notes in Computer Science},
  volume       = {3728},
  pages        = {666--673},
  publisher    = {Springer},
  year         = {2005},
  url          = {https://doi.org/10.1007/11556930\_68},
  doi          = {10.1007/11556930\_68},
  timestamp    = {Tue, 14 May 2019 10:00:54 +0200},
  biburl       = {https://dblp.org/rec/conf/patmos/VeredasC05.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}