BibTeX record conf/socc/ChungLCJCTCHKHLK14

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@inproceedings{DBLP:conf/socc/ChungLCJCTCHKHLK14,
  author       = {Chao{-}Kuei Chung and
                  Chien{-}Yu Lu and
                  Zhi{-}Hao Chang and
                  Shyh{-}Jye Jou and
                  Ching{-}Te Chuang and
                  Ming{-}Hsien Tu and
                  Yu{-}Hsian Chen and
                  Yong{-}Jyun Hu and
                  Paul{-}Sen Kan and
                  Huan{-}Shun Huang and
                  Kuen{-}Di Lee and
                  Yung{-}Shin Kao},
  editor       = {Kaijian Shi and
                  Thomas B{\"{u}}chner and
                  Danella Zhao and
                  Ramalingam Sridhar},
  title        = {A 40nm 256kb 6T {SRAM} with threshold power-gating, low-swing global
                  read bit-line, and charge-sharing write with Vtrip-tracking and negative
                  source-line write-assists},
  booktitle    = {27th {IEEE} International System-on-Chip Conference, {SOCC} 2014,
                  Las Vegas, NV, USA, September 2-5, 2014},
  pages        = {455--462},
  publisher    = {{IEEE}},
  year         = {2014},
  url          = {https://doi.org/10.1109/SOCC.2014.6948972},
  doi          = {10.1109/SOCC.2014.6948972},
  timestamp    = {Wed, 16 Oct 2019 14:14:53 +0200},
  biburl       = {https://dblp.org/rec/conf/socc/ChungLCJCTCHKHLK14.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}