BibTeX record conf/vlsi/AmaravatiCR15a

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@inproceedings{DBLP:conf/vlsi/AmaravatiCR15a,
  author    = {Anvesha Amaravati and
               Manan Chugh and
               Arijit Raychowdhury},
  title     = {A {SAR} Pipeline {ADC} Embedding Time Interleaved {DAC} Sharing for
               Ultra-low Power Camera Front Ends},
  booktitle = {VLSI-SoC: Design for Reliability, Security, and Low Power - 23rd {IFIP}
               {WG} 10.5/IEEE International Conference on Very Large Scale Integration,
               VLSI-SoC 2015, Daejeon, Korea, October 5-7, 2015, Revised Selected
               Papers},
  pages     = {131--149},
  year      = {2015},
  crossref  = {DBLP:conf/vlsi/2015socs},
  url       = {https://doi.org/10.1007/978-3-319-46097-0\_7},
  doi       = {10.1007/978-3-319-46097-0\_7},
  timestamp = {Tue, 22 Oct 2019 15:21:19 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/vlsi/AmaravatiCR15a},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/vlsi/2015socs,
  editor    = {Youngsoo Shin and
               Chi{-}Ying Tsui and
               Jae{-}Joon Kim and
               Kiyoung Choi and
               Ricardo Reis},
  title     = {VLSI-SoC: Design for Reliability, Security, and Low Power - 23rd {IFIP}
               {WG} 10.5/IEEE International Conference on Very Large Scale Integration,
               VLSI-SoC 2015, Daejeon, Korea, October 5-7, 2015, Revised Selected
               Papers},
  series    = {{IFIP} Advances in Information and Communication Technology},
  volume    = {483},
  publisher = {Springer},
  year      = {2016},
  url       = {https://doi.org/10.1007/978-3-319-46097-0},
  doi       = {10.1007/978-3-319-46097-0},
  isbn      = {978-3-319-46096-3},
  timestamp = {Tue, 22 Oct 2019 15:21:19 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/vlsi/2015socs},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
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