BibTeX record conf/vlsi/JiangDY06

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@inproceedings{DBLP:conf/vlsi/JiangDY06,
  author       = {Shan Jiang and
                  Manh Anh Do and
                  Kiat Seng Yeo},
  title        = {A 200-MHz {CMOS} Mixed-Mode Sample-and-Hold Circuit for Pipelined
                  ADCs},
  booktitle    = {{IFIP} VLSI-SoC 2006, {IFIP} {WG} 10.5 International Conference on
                  Very Large Scale Integration of System-on-Chip, Nice, France, 16-18
                  October 2006},
  pages        = {352--356},
  publisher    = {{IEEE}},
  year         = {2006},
  url          = {https://doi.org/10.1109/VLSISOC.2006.313260},
  doi          = {10.1109/VLSISOC.2006.313260},
  timestamp    = {Sun, 25 Jul 2021 11:51:38 +0200},
  biburl       = {https://dblp.org/rec/conf/vlsi/JiangDY06.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
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