BibTeX record conf/vlsic/ChenYSHTH19

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@inproceedings{DBLP:conf/vlsic/ChenYSHTH19,
  author       = {Wei{-}Chih Chen and
                  Shu{-}Chun Yang and
                  Yu{-}Nan Shih and
                  Wen{-}Hung Huang and
                  Chien{-}Chun Tsai and
                  Kenny Cheng{-}Hsiang Hsieh},
  title        = {A 56Gb/s {PAM-4} Receiver with Voltage Pre-Shift {CTLE} and 10-Tap
                  {DFE} of Tap-1 Speculation in 7nm FinFET},
  booktitle    = {2019 Symposium on {VLSI} Circuits, Kyoto, Japan, June 9-14, 2019},
  pages        = {272},
  publisher    = {{IEEE}},
  year         = {2019},
  url          = {https://doi.org/10.23919/VLSIC.2019.8777992},
  doi          = {10.23919/VLSIC.2019.8777992},
  timestamp    = {Wed, 16 Oct 2019 14:14:49 +0200},
  biburl       = {https://dblp.org/rec/conf/vlsic/ChenYSHTH19.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}