BibTeX record conf/vlsic/TanakaIYSTTNS14

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@inproceedings{DBLP:conf/vlsic/TanakaIYSTTNS14,
  author       = {Shinji Tanaka and
                  Yuichiro Ishii and
                  Makoto Yabuuchi and
                  Toshiaki Sano and
                  Koji Tanaka and
                  Yasumasa Tsukamoto and
                  Koji Nii and
                  Hirotoshi Sato},
  title        = {A 512-kb 1-GHz 28-nm partially write-assisted dual-port {SRAM} with
                  self-adjustable negative bias bitline},
  booktitle    = {Symposium on {VLSI} Circuits, {VLSIC} 2014, Digest of Technical Papers,
                  Honolulu, HI, USA, June 10-13, 2014},
  pages        = {1--2},
  publisher    = {{IEEE}},
  year         = {2014},
  url          = {https://doi.org/10.1109/VLSIC.2014.6858411},
  doi          = {10.1109/VLSIC.2014.6858411},
  timestamp    = {Wed, 16 Oct 2019 14:14:49 +0200},
  biburl       = {https://dblp.org/rec/conf/vlsic/TanakaIYSTTNS14.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}