BibTeX record conf/vlsic/WeiSSYK15

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@inproceedings{DBLP:conf/vlsic/WeiSSYK15,
  author       = {Guowen Wei and
                  Pradeep Shettigar and
                  Feng Su and
                  Xinyu Yu and
                  Tom Kwan},
  title        = {A 13-ENOB, 5 MHz BW, 3.16 mW multi-bit continuous-time {\(\Delta\)}{\(\Sigma\)}
                  {ADC} in 28 nm {CMOS} with excess-loop-delay compensation embedded
                  in {SAR} quantizer},
  booktitle    = {Symposium on {VLSI} Circuits, {VLSIC} 2015, Kyoto, Japan, June 17-19,
                  2015},
  pages        = {292},
  publisher    = {{IEEE}},
  year         = {2015},
  url          = {https://doi.org/10.1109/VLSIC.2015.7231295},
  doi          = {10.1109/VLSIC.2015.7231295},
  timestamp    = {Wed, 16 Oct 2019 14:14:49 +0200},
  biburl       = {https://dblp.org/rec/conf/vlsic/WeiSSYK15.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}