BibTeX record conf/vlsid/KumarVKS16

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@inproceedings{DBLP:conf/vlsid/KumarVKS16,
  author       = {Ashish Kumar and
                  G. S. Visweswaran and
                  Vinay Kumar and
                  Kaushik Saha},
  title        = {A 0.5V {VMIN} 6T {SRAM} in 28nm {UTBB} {FDSOI} Technology Using Compensated
                  {WLUD} Scheme with Zero Performance Loss},
  booktitle    = {29th International Conference on {VLSI} Design and 15th International
                  Conference on Embedded Systems, {VLSID} 2016, Kolkata, India, January
                  4-8, 2016},
  pages        = {191--195},
  publisher    = {{IEEE} Computer Society},
  year         = {2016},
  url          = {https://doi.org/10.1109/VLSID.2016.62},
  doi          = {10.1109/VLSID.2016.62},
  timestamp    = {Fri, 24 Mar 2023 00:04:01 +0100},
  biburl       = {https://dblp.org/rec/conf/vlsid/KumarVKS16.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
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