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BibTeX record conf/vlsid/MallyaPR15
@inproceedings{DBLP:conf/vlsid/MallyaPR15, author = {Neethu Bal Mallya and Geeta Patil and Biju K. Raveendran}, title = {Way Halted Prediction Cache: An Energy Efficient Cache Architecture for Embedded Processors}, booktitle = {28th International Conference on {VLSI} Design, {VLSID} 2015, Bangalore, India, January 3-7, 2015}, pages = {65--70}, publisher = {{IEEE} Computer Society}, year = {2015}, url = {https://doi.org/10.1109/VLSID.2015.16}, doi = {10.1109/VLSID.2015.16}, timestamp = {Fri, 24 Mar 2023 00:03:59 +0100}, biburl = {https://dblp.org/rec/conf/vlsid/MallyaPR15.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
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