BibTeX record journals/ieiceee/JiangHWWM15

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@article{DBLP:journals/ieiceee/JiangHWWM15,
  author       = {Jianfei Jiang and
                  Weifeng He and
                  Jizeng Wei and
                  Qin Wang and
                  Zhigang Mao},
  title        = {Design optimization for capacitive-resistively driven on-chip global
                  interconnect},
  journal      = {{IEICE} Electron. Express},
  volume       = {12},
  number       = {8},
  pages        = {20150111},
  year         = {2015},
  url          = {https://doi.org/10.1587/elex.12.20150111},
  doi          = {10.1587/ELEX.12.20150111},
  timestamp    = {Wed, 22 Jun 2022 14:34:18 +0200},
  biburl       = {https://dblp.org/rec/journals/ieiceee/JiangHWWM15.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
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