BibTeX record journals/jssc/WuYGNCHZVLSC19

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@article{DBLP:journals/jssc/WuYGNCHZVLSC19,
  author       = {Wanghua Wu and
                  Chih{-}Wei Yao and
                  Kunal Godbole and
                  Ronghua Ni and
                  Pei{-}Yuan Chiang and
                  Yongping Han and
                  Yongrong Zuo and
                  Ashutosh Verma and
                  Ivan Siu{-}Chuang Lu and
                  Sang Won Son and
                  Thomas Byunghak Cho},
  title        = {A 28-nm 75-fs\({}_{\mbox{rms}}\) Analog Fractional- {\textdollar}N{\textdollar}
                  Sampling {PLL} With a Highly Linear {DTC} Incorporating Background
                  {DTC} Gain Calibration and Reference Clock Duty Cycle Correction},
  journal      = {{IEEE} J. Solid State Circuits},
  volume       = {54},
  number       = {5},
  pages        = {1254--1265},
  year         = {2019},
  url          = {https://doi.org/10.1109/JSSC.2019.2899726},
  doi          = {10.1109/JSSC.2019.2899726},
  timestamp    = {Sun, 30 Aug 2020 00:13:56 +0200},
  biburl       = {https://dblp.org/rec/journals/jssc/WuYGNCHZVLSC19.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}