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BibTeX record journals/tcad/WangTJ03
@article{DBLP:journals/tcad/WangTJ03, author = {Chun{-}Yao Wang and Shing{-}Wu Tung and Jing{-}Yang Jou}, title = {Automatic interconnection rectification for SoC design verification based on the port order fault model}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {22}, number = {1}, pages = {104--114}, year = {2003}, url = {https://doi.org/10.1109/TCAD.2002.805723}, doi = {10.1109/TCAD.2002.805723}, timestamp = {Thu, 24 Sep 2020 11:27:16 +0200}, biburl = {https://dblp.org/rec/journals/tcad/WangTJ03.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
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