BibTeX record journals/tcas/ZhengWLZYZW16

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@article{DBLP:journals/tcas/ZhengWLZYZW16,
  author    = {Xuqiang Zheng and
               Zhijun Wang and
               Fule Li and
               Feng Zhao and
               Shigang Yue and
               Chun Zhang and
               Zhihua Wang},
  title     = {A 14-bit 250 MS/s {IF} Sampling Pipelined {ADC} in 180 nm {CMOS} Process},
  journal   = {{IEEE} Trans. on Circuits and Systems},
  volume    = {63-I},
  number    = {9},
  pages     = {1381--1392},
  year      = {2016},
  url       = {https://doi.org/10.1109/TCSI.2016.2580703},
  doi       = {10.1109/TCSI.2016.2580703},
  timestamp = {Sat, 03 Nov 2018 00:15:22 +0100},
  biburl    = {https://dblp.org/rec/bib/journals/tcas/ZhengWLZYZW16},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
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