BibTeX record journals/wpc/UdaiyakumarJSVM18

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@article{DBLP:journals/wpc/UdaiyakumarJSVM18,
  author       = {R. Udaiyakumar and
                  Senoj Joseph and
                  T. V. P. Sundararajan and
                  Dhasarathan Vigneswaran and
                  R. Maheswar and
                  Iraj S. Amiri},
  title        = {Self Clock-Gating Scheme for Low Power Basic Logic Element Architecture},
  journal      = {Wirel. Pers. Commun.},
  volume       = {102},
  number       = {4},
  pages        = {3477--3488},
  year         = {2018},
  url          = {https://doi.org/10.1007/s11277-018-5385-2},
  doi          = {10.1007/S11277-018-5385-2},
  timestamp    = {Thu, 14 Oct 2021 09:31:22 +0200},
  biburl       = {https://dblp.org/rec/journals/wpc/UdaiyakumarJSVM18.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
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