BibTeX record conf/iscas/WangWLW18

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@inproceedings{DBLP:conf/iscas/WangWLW18,
  author    = {Xiao Wang and
               Chengwei Wang and
               Fule Li and
               Zhihua Wang},
  title     = {A Low-Power 12-bit 2GS/s Time-Interleaved Pipelined-SAR {ADC} in 28nm
               {CMOS} Process},
  booktitle = {{IEEE} International Symposium on Circuits and Systems, {ISCAS} 2018,
               27-30 May 2018, Florence, Italy},
  pages     = {1--5},
  publisher = {{IEEE}},
  year      = {2018},
  url       = {https://doi.org/10.1109/ISCAS.2018.8351064},
  doi       = {10.1109/ISCAS.2018.8351064},
  timestamp = {Wed, 16 Oct 2019 14:14:49 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/iscas/WangWLW18},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
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