"A 2.5Gb/s oversampling clock and data recovery circuit with frequency ..."

Kai Pong Wu, Ching-Yuan Yang, Jung-Mao Lin (2008)

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DOI: 10.1109/APCCAS.2008.4746280

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-17

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Kai Pong Wu, Ching-Yuan Yang, Jung-Mao Lin:
A 2.5Gb/s oversampling clock and data recovery circuit with frequency calibration technique. APCCAS 2008: 1356-1359

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