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"Design and Validation of a FPGA-Based HIL Simulator for Minimum Losses ..."

Giuseppe Galioto, Antonino Sferlazza, Giuseppe Costantino Giaconia (2020)

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DOI: 10.1007/978-3-030-66729-0_18

access: closed

type: Conference or Workshop Paper

metadata version: 2022-04-09

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  dblp key:
  - conf/applepies/GaliotoSG20
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  - https://dblp.org/rec/conf/applepies/GaliotoSG20
Giuseppe Galioto, Antonino Sferlazza, Giuseppe Costantino Giaconia:
Design and Validation of a FPGA-Based HIL Simulator for Minimum Losses Control of a PMSM. ApplePies 2020: 152-163

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