"Design of high speed MOS multiplier and divider using redundant binary ..."

Shigeo Kuninobu et al. (1987)

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DOI: 10.1109/ARITH.1987.6158706

access: closed

type: Conference or Workshop Paper

metadata version: 2020-12-29

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Shigeo Kuninobu, Tamotsu Nishiyama, Hisakazu Edamatsu, Takashi Taniguchi, Naofumi Takagi:
Design of high speed MOS multiplier and divider using redundant binary representation. IEEE Symposium on Computer Arithmetic 1987: 80-86

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