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"Parallel sparse LU decomposition using FPGA with an efficient cache ..."

Xiang Ge et al. (2017)

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DOI: 10.1109/ASICON.2017.8252462

access: closed

type: Conference or Workshop Paper

metadata version: 2018-01-17

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  dblp key:
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Xiang Ge, Hengliang Zhu, Fan Yang, Lingli Wang, Xuan Zeng:
Parallel sparse LU decomposition using FPGA with an efficient cache architecture. ASICON 2017: 259-262

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