"A fully pipelined hardware architecture for convolutional neural network ..."

Zhiwei Li et al. (2017)

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DOI: 10.1109/ASICON.2017.8252456

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type: Conference or Workshop Paper

metadata version: 2024-08-15

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Zhiwei Li, Yan Li, Song Chen, Feng Wu:
A fully pipelined hardware architecture for convolutional neural network with low memory usage and DRAM bandwidth. ASICON 2017: 237-240

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