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"A method to speed up VLSI hierarchical physical design in floorplanning."

Yanling Zhou, Yunyao Yan, Wei Yan (2017)

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DOI: 10.1109/ASICON.2017.8252484

access: closed

type: Conference or Workshop Paper

metadata version: 2018-01-17

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  dblp key:
  - conf/asicon/ZhouYY17
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  - https://dblp.org/rec/conf/asicon/ZhouYY17
Yanling Zhou, Yunyao Yan, Wei Yan:
A method to speed up VLSI hierarchical physical design in floorplanning. ASICON 2017: 347-350

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