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"An optimal gate design for the synthesis of ternary logic circuits."

Sunmean Kim, Taeho Lim, Seokhyeong Kang (2018)

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DOI: 10.1109/ASPDAC.2018.8297369

access: closed

type: Conference or Workshop Paper

metadata version: 2019-10-19

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  dblp key:
  - conf/aspdac/KimLK18
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  persistent URL:
  - https://dblp.org/rec/conf/aspdac/KimLK18
Sunmean Kim, Taeho Lim, Seokhyeong Kang:
An optimal gate design for the synthesis of ternary logic circuits. ASP-DAC 2018: 476-481

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