"A 16-bit redundant binary multiplier using low-power pass-transistor logic ..."

Hirofumi Sakamoto et al. (2000)

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DOI: 10.1145/368434.368495

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-23

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Hirofumi Sakamoto, Ken'ichiro Uda, Bu-Yeol Lee, Hiroyuki Ochi, Kazuo Taki, Takao Tsuda:
A 16-bit redundant binary multiplier using low-power pass-transistor logic SPL. ASP-DAC 2000: 33-34

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