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"Statistical timing verification for transparently latched circuits through ..."

Xingliang Yuan, Jia Wang (2010)

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DOI: 10.1109/ASPDAC.2010.5419803

access: closed

type: Conference or Workshop Paper

metadata version: 2018-11-02

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  - https://dblp.org/rec/conf/aspdac/YuanW10
Xingliang Yuan, Jia Wang:
Statistical timing verification for transparently latched circuits through structural graph traversal. ASP-DAC 2010: 663-668

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