"PLD: fast FPGA compilation to make reconfigurable acceleration compatible ..."

Yuanlong Xiao et al. (2022)

> Home

Details and statistics

DOI: 10.1145/3503222.3507740

access: closed

type: Conference or Workshop Paper

metadata version: 2025-01-19

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/asplos/XiaoMBHAGMD22
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/asplos/XiaoMBHAGMD22
Yuanlong Xiao, Eric Micallef, Andrew Butt, Matthew Hofmann, Marc Alston, Matthew Goldsmith, Andrew Merczynski-Hait, André DeHon:
PLD: fast FPGA compilation to make reconfigurable acceleration compatible with modern incremental refinement software development. ASPLOS 2022: 933-945

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.