"A 5.92-Mb/mm2 28-nm pseudo 2-read/write dual-port SRAM using ..."

Yuichiro Ishii et al. (2016)

> Home

Details and statistics

DOI: 10.1109/ASSCC.2016.7844124

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-24

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/asscc/IshiiYSMTYSSTN16
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/asscc/IshiiYSMTYSSTN16
Yuichiro Ishii, Makoto Yabuuchi, Yohei Sawada, Masao Morimoto, Yasumasa Tsukamoto, Yuta Yoshida, Ken Shibata, Toshiaki Sano, Shinji Tanaka, Koji Nii:
A 5.92-Mb/mm² 28-nm pseudo 2-read/write dual-port SRAM using double pumping circuitry. A-SSCC 2016: 17-20

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.