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"A 21-Gb/s, 0.96-pJ/bit serial receiver with non-50% duty-cycle clocking ..."

Yang You et al. (2015)

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DOI: 10.1109/ASSCC.2015.7387469

access: closed

type: Conference or Workshop Paper

metadata version: 2018-10-15

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Yang You, Sudipto Chakraborty, Rui Wang, Jinghong Chen:
A 21-Gb/s, 0.96-pJ/bit serial receiver with non-50% duty-cycle clocking 1-tap decision feedback equalizer in 65nm CMOS. A-SSCC 2015: 1-4

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